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m pd780973 subseries 8-bit single-chip microcontrollers m pd780973(a) m pd78f0974 document no. u12406ej2v0um00 (2nd edition) date published may 1998 n cp(k) 1997 preliminary user? manual printed in japan
2 [memo]
3 eeprom, fip, and iebus are trademarks of nec corporation. windows and windowsnt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. ethernet is a trademark of xerox corporation. news and news-os are trademarks of sony corporation. osf/motif is a trademark of opensoftware foundation, inc. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
4 the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 this product is produced and sold based on the licensed agreement with cp8 transac concerning eeprom- contained microcontroller. this product cannot be used for an ic card (smart card). the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. license not needed : m pd78f0974gf-3b9 the customer must judge the need for license : m pd780973gf(a)- -3b9 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.
5 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j98. 2
6 major revisions in this edition (1/2) page description p.38 table 2-1. pin input/output circuit types correction of ports 8 and 9 input/output circuit types p.40 figure 2-1. i/o circuits of pins change of type 17-a to type 17-g p.54 addition of oscillator mode register to table 3-5. special function register list p.67 4.1 eeprom functions change of the number of rewrite frequency per 1 byte as follows: 10,000 times ? 100,000 times p.77 5.2.3 port 2 ? correction of description ? correction of figure 5-4. p20 to p27 block diagram p.78 5.2.4 port 3 ? correction of description ? correction of figure 5-5. p30 to p37 block diagram p.82 5.2.8 port 8 ? correction of description ? addition of figure 5-9. p81 block diagram ? correction of figure 5-10. p82 to p87 block diagram p.83 5.2.9 port 9 ? correction of description ? correction of figure 5-11. p90 to p97 block diagram p.85 table 5-3. port mode register and output latch settings when using alternate functions ? change of p setting values of p20 to p27 and p30 to p37 from 0 to change of note 2 p.86 addition of note in figure 5-13. port mode register (pm2, pm3) format p.89 chapter 6 clock generator ? addition of oscillator mode register to table 6-1. clock generator configuration ? change of figure 6-1. clock generator block diagram ? addition of (2) oscillator mode register (oscm) to 6.3 clock generator control register ? addition of explanation of oscillator mode register to 6.5 operation of clock generator p.163 13.6 cautions on emulation change of in-circuit emulator of (1) d/a converter mode register (dam1) as follows: ie-78001-r-a ? ie78k0-ns addition of (2) a/d converter of ie-780974-ns-em1 p.203 16.9 cautions on emulation change of in-circuit emulator of (1) lcd timer control register (lcdtm) as follows: ie-78001-r-a ? ie78k0-ns p.205 17.1 sound generator function correction of description on (1) basic cycle output signal (with/without amplitude) p.214 18.2 meter controller/driver configuration addition of cautions to (1) free running up counter (mcnt) p.247 table 20-1. halt mode operating status correction of halt mode operating status of a/d converter operable ? operation stops the mark shows major revised points.
7 major revisions in this edition (2/2) page description p.255 addition of oscillator mode register to table 21-1. hardware status after reset p.257 change of note in table 22-1. differences between m pd78f0974 and m pd780973(a) p.279 appendix a development tools ? support of in-circuit emulator ie-78k0-ns ? change in supported os ? addition of a.4 upgrading former in-circuit emulator for 78k/0 series to ie-78001-r-a ? deletion of os for ibm pc from previous edition ? deletion of development environment when using ie-78000-r-a from previous edition p.291 appendix b embedded software ? change in supported os ? deletion of fuzzy inference development support system from previous edition the mark shows major revised points.
8 introduction readers this manual has been prepared for user engineers who want to understand the functions of the m pd780973 subseries and design and develop its application systems and programs. purpose this manual is designed to help users understand the following functions using the organization below. organization the m pd780973 subseries manual is separated into two parts: this manual and the instruction edition (common to the 78k/0 series). m pd780973 subseries 78k/0 series users manual users manual (this manual) instructions ? pin functions ? cpu functions ? internal block functions ? instruction set ? interrupt ? explanation of each instruction ? other on-chip peripheral functions how to read this manual this manual assumes general knowledge of electric engineering, logic circuits, and microcontrollers. ? to understand the functions of the m pd780973(a) and 78f0974 in general: ? read this manual in the order of the contents . ? how to read register formats: ? the name of a bit whose number is enclosed in square is reserved for the ra78k/ 0 and is defined for the cc78k/0 by the header file sfrbit.h. ? to learn the detailed functions of a register whose register name is known: ? refer to appendix c register index . the application examples in this manual are for the standard model for general- purpose electronic systems. if the examples in this manual are to be used for applications where a quality higher than that of the special model is required, study the quality grade of the respective components and circuits actually used. conventions data significance : higher digits on the left and lower digits on the right active low representation : (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation : binary or b decimal hexadecimal h
9 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? related documents for m pd780973 subseries document name document no. japanese english m pd780973(a) preliminary product information u12759j u12759e m pd78f0974 preliminary product information u12646j u12646e m pd780973 subseries users manual u12406j this manual 78k/0 series users manual instructions u12326j u12326e 78k/0 series instruction table u10903j 78k/0 series instruction set u10904j m pd780973 subseries special function register table u12748j ? related documents for development tool (users manual) document name document no. japanese english ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly language u11789j u11789e ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e cc78k/0 c compiler application note programming know-how u13034j eea-1208 cc78k series library source file u12322j ie-78k0-ns to be prepared to be prepared ie-78001-r-a to be prepared to be prepared sm78k0 system simulator windows tm base reference u10181j u10181e sm78k series system simulator external part user open u10092j u10092e interface specifications id78k0-ns integrated debugger pc base reference u12900j to be prepared id78k0 integrated debugger ews base reference u11151j id78k0 integrated debugger pc base reference u11539j u11539e id78k0 integrated debugger windows base guide u11649j u11649e caution the above documents are subject to change without prior notice. be sure to use the latest version of a document when starting design.
10 ? related documents for embedded software (users manual) document name document no. japanese english 78k/0 series real-time os basics u11537j u11537e installation u11536j u11536e 78k/0 series os mx78k0 basics u12257j u12257e ? other related documents document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electro static discharge (esd) c11892j c11892e guide to quality assurance for semiconductor devices mei-1202 microcomputer product series guide u11416j caution the above documents are subject to change without prior notice. be sure to use the latest version of a document when starting design.
11 contents chapter 1 outline .............................................................................................................. ...... 23 1.1 features .................................................................................................................... ............ 23 1.2 applications ................................................................................................................ ......... 23 1.3 ordering information ........................................................................................................ ... 24 1.4 quality grade ............................................................................................................... ........ 24 1.5 pin configuration (top view) ............................................................................................. 25 1.6 78k/0 series product development ................................................................................... 27 1.7 block diagram ............................................................................................................... ....... 29 1.8 outline of function ......................................................................................................... ..... 30 chapter 2 pin function ........................................................................................................ .. 31 2.1 pin function list ........................................................................................................... ....... 31 2.2 description of pin functions .............................................................................................. 33 2.2.1 p00 to p07 (port 0) ....................................................................................................... .............. 33 2.2.2 p10 to p14 (port 1) ....................................................................................................... .............. 33 2.2.3 p20 to p27 (port 2) ....................................................................................................... .............. 33 2.2.4 p30 to p37 (port 3) ....................................................................................................... .............. 34 2.2.5 p40 to p44 (port 4) ....................................................................................................... .............. 34 2.2.6 p50 to p54 (port 5) ....................................................................................................... .............. 34 2.2.7 p60, p61 (port 6) ......................................................................................................... ............... 35 2.2.8 p81 to p87 (port 8) ....................................................................................................... .............. 35 2.2.9 p90 to p97 (port 9) ....................................................................................................... .............. 36 2.2.10 com0 to com3 ............................................................................................................. ............. 36 2.2.11 v lcd ............................................................................................................................... .............. 36 2.2.12 av ref ............................................................................................................................... ........... 36 2.2.13 av ss ............................................................................................................................... ............. 36 2.2.14 reset .................................................................................................................... .................... 36 2.2.15 x1 and x2 ................................................................................................................ ................... 36 2.2.16 smv dd ............................................................................................................................... .......... 36 2.2.17 smv ss ............................................................................................................................... .......... 36 2.2.18 v dd ............................................................................................................................... ............... 36 2.2.19 v ss ............................................................................................................................... ............... 36 2.2.20 v pp ( m pd78f0974) ..................................................................................................................... .37 2.2.21 ic ( m pd780973(a)) ................................................................................................................... .. 37 2.3 input/output circuits and recommended connection of unused pins ......................... 38 chapter 3 cpu architecture .............................................................................................. 41 3.1 memory spaces ............................................................................................................... .... 41 3.1.1 internal program memory space ............................................................................................. .... 43 3.1.2 internal data memory space ................................................................................................ ....... 44 3.1.3 special function register (sfr) area ...................................................................................... ..... 44 3.1.4 data memory addressing .................................................................................................... ........ 45 3.2 processor registers ......................................................................................................... ... 47 3.2.1 control registers ......................................................................................................... ................ 47 3.2.2 general registers ......................................................................................................... ............... 50
12 3.2.3 special function registers (sfrs) ......................................................................................... ...... 51 3.3 instruction address addressing ........................................................................................ 55 3.3.1 relative addressing ....................................................................................................... ............. 55 3.3.2 immediate addressing ...................................................................................................... .......... 56 3.3.3 table indirect addressing ................................................................................................. ........... 57 3.3.4 register addressing ....................................................................................................... ............. 57 3.4 operand address addressing ............................................................................................ 58 3.4.1 implied addressing ........................................................................................................ .............. 58 3.4.2 register addressing ....................................................................................................... ............. 59 3.4.3 direct addressing ......................................................................................................... ............... 60 3.4.4 short direct addressing ................................................................................................... ............ 61 3.4.5 special-function register (sfr) addressing ................................................................................ 62 3.4.6 register indirect addressing .............................................................................................. ......... 63 3.4.7 based addressing .......................................................................................................... ............. 64 3.4.8 based indexed addressing .................................................................................................. ....... 64 3.4.9 stack addressing .......................................................................................................... .............. 65 chapter 4 eeprom ............................................................................................................... ...... 67 4.1 eeprom functions ............................................................................................................ .67 4.2 eeprom configuration ....................................................................................................... 6 8 4.3 eeprom control register .................................................................................................. 69 4.4 eeprom reading .............................................................................................................. .. 70 4.5 eeprom writing .............................................................................................................. .... 71 4.6 eeprom control-related interrupt ................................................................................... 71 4.7 cautions regarding eeprom writing ................................................................................ 72 chapter 5 port functions ................................................................................................... 73 5.1 port functions .............................................................................................................. ....... 73 5.2 port configuration .......................................................................................................... ..... 75 5.2.1 port 0 .................................................................................................................... ...................... 75 5.2.2 port 1 .................................................................................................................... ...................... 76 5.2.3 port 2 .................................................................................................................... ...................... 77 5.2.4 port 3 .................................................................................................................... ...................... 78 5.2.5 port 4 .................................................................................................................... ...................... 79 5.2.6 port 5 .................................................................................................................... ...................... 80 5.2.7 port 6 .................................................................................................................... ...................... 81 5.2.8 port 8 .................................................................................................................... ...................... 82 5.2.9 port 9 .................................................................................................................... ...................... 83 5.3 port function control registers ........................................................................................ 84 5.4 port function operations ................................................................................................... 8 8 5.4.1 writing to input/output port .............................................................................................. ............ 88 5.4.2 reading from input/output port ............................................................................................ ....... 88 5.4.3 operations on input/output port ........................................................................................... ....... 88 chapter 6 clock generator .............................................................................................. 89 6.1 clock generator functions ................................................................................................. 89 6.2 clock generator configuration .......................................................................................... 89 6.3 clock generator control register ...................................................................................... 90
13 6.4 system clock oscillator ..................................................................................................... .92 6.4.1 main system clock oscillator .............................................................................................. ......... 92 6.4.2 divider circuit ........................................................................................................... ................... 94 6.5 operation of clock generator ............................................................................................ 95 6.6 changing setting of cpu clock ......................................................................................... 96 6.6.1 time required for switching cpu clock ..................................................................................... .. 96 6.6.2 switching cpu clock ....................................................................................................... ............ 97 chapter 7 16-bit timer 0 tm0 ............................................................................................... 9 9 7.1 outline of internal timer of m pd780973 subseries ........................................................... 99 7.2 16-bit timer 0 functions .................................................................................................... . 100 7.3 16-bit timer 0 configuration .............................................................................................. 10 2 7.4 16-bit timer 0 control registers ........................................................................................ 103 7.5 16-bit timer 0 operations ................................................................................................... 106 7.5.1 pulse width measurement operations ........................................................................................ . 106 7.6 16-bit timer 0 cautions ..................................................................................................... .. 109 chapter 8 8-bit timer 1 tm1 ................................................................................................. 111 8.1 8-bit timer 1 functions ..................................................................................................... .. 111 8.2 8-bit timer 1 configuration ................................................................................................ 1 12 8.3 8-bit timer 1 control registers .......................................................................................... 113 8.4 8-bit timer 1 operations .................................................................................................... . 115 8.4.1 8-bit interval timer operation ............................................................................................ ........... 115 8.5 8-bit timer 1 cautions ...................................................................................................... ... 118 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 .............................................. 119 9.1 8-bit timer/event counters 2 and 3 functions ................................................................. 119 9.2 8-bit timer/event counters 2 and 3 configurations ........................................................ 121 9.3 8-bit timer/event counters 2 and 3 control registers .................................................... 122 9.4 8-bit timer/event counters 2 and 3 operations ............................................................... 125 9.4.1 8-bit interval timer operation ............................................................................................ ........... 125 9.4.2 external event counter operation .......................................................................................... ...... 127 9.4.3 square-wave output operation (8-bit resolution) ......................................................................... 12 8 9.4.4 8-bit pwm output operation ................................................................................................ ........ 129 9.5 8-bit timer/event counters 2 and 3 cautions ................................................................... 132 chapter 10 watch timer ........................................................................................................ .. 133 10.1 watch timer functions ...................................................................................................... . 133 10.2 watch timer configuration ................................................................................................. 1 34 10.3 watch timer control register ............................................................................................ 135 10.4 watch timer operations ..................................................................................................... 136 10.4.1 watch timer operation .................................................................................................... ............. 136 10.4.2 interval timer operation ................................................................................................. .............. 136 chapter 11 watchdog timer ................................................................................................. 139 11.1 watchdog timer functions ................................................................................................ 139 11.2 watchdog timer configuration .......................................................................................... 141 11.3 watchdog timer control registers ................................................................................... 141
14 11.4 watchdog timer operations ............................................................................................... 143 11.4.1 watchdog timer operation ................................................................................................. .......... 143 11.4.2 interval timer operation ................................................................................................. .............. 144 chapter 12 clock output control circuit .................................................................. 145 12.1 clock output control circuit functions ............................................................................ 145 12.2 clock output control circuit configuration ..................................................................... 145 12.3 clock output control circuit control registers ............................................................... 146 12.4 clock output control circuit operation ............................................................................ 148 12.4.1 clock output operation ................................................................................................... ............. 148 chapter 13 a/d converter ..................................................................................................... 1 49 13.1 a/d converter functions .................................................................................................... 149 13.2 a/d converter configuration .............................................................................................. 15 0 13.3 a/d converter control registers ....................................................................................... 152 13.4 a/d converter operations ................................................................................................... 155 13.4.1 basic operations of a/d converter ........................................................................................ ...... 155 13.4.2 input voltage and conversion results ..................................................................................... ..... 157 13.4.3 a/d converter operation mode ............................................................................................. ....... 158 13.5 a/d converter cautions ..................................................................................................... . 160 13.6 cautions on emulation ...................................................................................................... .. 163 chapter 14 serial interface uart .................................................................................... 165 14.1 uart functions ............................................................................................................. ...... 165 14.2 uart configuration ......................................................................................................... ... 166 14.3 uart control registers ..................................................................................................... . 167 14.4 uart operations ............................................................................................................ ..... 171 14.4.1 operation stop mode ...................................................................................................... ............ 171 14.4.2 asynchronous serial interface (uart) mode ............................................................................. 171 chapter 15 serial interface sio3 ...................................................................................... 183 15.1 sio3 functions ............................................................................................................. ....... 183 15.2 sio3 configuration ......................................................................................................... ..... 184 15.3 sio3 control register ...................................................................................................... ... 185 15.4 sio3 operations ............................................................................................................ ....... 186 15.4.1 operation stop mode ...................................................................................................... ............ 186 15.4.2 three-wire serial i/o mode ............................................................................................... .......... 187 chapter 16 lcd controller/driver ................................................................................... 189 16.1 lcd controller/driver functions ........................................................................................ 189 16.2 lcd controller/driver configuration ................................................................................. 190 16.3 lcd controller/driver control registers ........................................................................... 192 16.4 lcd controller/driver settings ........................................................................................... 19 4 16.5 lcd display data memory .................................................................................................. 19 5 16.6 common signals and segment signals ............................................................................ 196 16.7 supplying lcd drive voltage v lc0 , v lc1 , and v lc2 ........................................................... 198 16.8 display mode ............................................................................................................... ......... 200 16.8.1 4-time-division display example .......................................................................................... ........ 200
15 16.9 cautions on emulation ...................................................................................................... .. 203 chapter 17 sound generator .............................................................................................. 205 17.1 sound generator function ................................................................................................. 20 5 17.2 sound generator configuration ......................................................................................... 206 17.3 sound generator control registers .................................................................................. 207 17.4 sound generator operations ............................................................................................. 212 17.4.1 to output basic cycle signal sgof (without amplitude) ............................................................. 212 17.4.2 to output basic cycle signal sgo (with amplitude) ..................................................................... 212 chapter 18 meter controller/driver .............................................................................. 213 18.1 meter controller/driver functions ..................................................................................... 213 18.2 meter controller/driver configuration ............................................................................... 214 18.3 meter controller/driver control registers ........................................................................ 216 18.4 meter controller/driver operations .................................................................................... 220 18.4.1 basic operation of free-running up counter (mcnt) ................................................................... 220 18.4.2 to update pwm data ....................................................................................................... ........... 220 18.4.3 operation of 1-bit addition circuit ...................................................................................... .......... 221 18.4.4 pwm output operation (output with 1 clock shifted) ................................................................... 222 chapter 19 interrupt functions ......................................................................................... 223 19.1 interrupt function types ................................................................................................... . 223 19.2 interrupt sources and configuration ................................................................................. 223 19.3 interrupt function control registers ................................................................................. 227 19.4 interrupt servicing operations ........................................................................................... 23 4 19.4.1 non-maskable interrupt request acknowledge operation ........................................................... 234 19.4.2 maskable interrupt request acknowledge operation ................................................................... 237 19.4.3 software interrupt request acknowledge operation .................................................................... 239 19.4.4 multiple interrupt servicing ............................................................................................. ............. 240 19.4.5 interrupt request hold ................................................................................................... ............... 243 chapter 20 standby function .............................................................................................. 245 20.1 standby function and configuration ................................................................................ 245 20.1.1 standby function ......................................................................................................... ................ 245 20.1.2 standby function control register ........................................................................................ ........ 246 20.2 standby function operations ............................................................................................ 247 20.2.1 halt mode ................................................................................................................ ................. 247 20.2.2 stop mode ................................................................................................................ ................ 250 chapter 21 reset function .................................................................................................... 2 53 21.1 reset function ............................................................................................................. ........ 253 chapter 22 m pd78f0974 ............................................................................................................... 257 22.1 memory size switching register ....................................................................................... 258 22.2 flash memory programming .............................................................................................. 259 22.2.1 selection of transmission method ......................................................................................... ...... 259 22.2.2 flash memory programming function ........................................................................................ . 260 22.2.3 flashpro ii connection ................................................................................................... ............. 260
16 chapter 23 instruction set ................................................................................................... 2 63 23.1 legend for operation list .................................................................................................. . 264 23.1.1 operand identifiers and description formats .............................................................................. . 264 23.1.2 description of operation column ........................................................................................ ....... 265 23.1.3 description of flag operation column ................................................................................... ..... 265 23.2 operation list ............................................................................................................. ......... 266 23.3 instructions listed by addressing type ........................................................................... 274 appendix a development tools .......................................................................................... 279 a.1 language processing software ......................................................................................... 282 a.2 flash memory writing tools ............................................................................................... 283 a.3 debugging tools ............................................................................................................. .... 284 a.3.1 hardware .................................................................................................................. .................. 284 a.3.2 software .................................................................................................................. .................... 286 a.4 upgrading former in-circuit emulator for 78k/0 series to ie-78001-r-a ....................... 288 appendix b embedded software ......................................................................................... 291 appendix c register index ..................................................................................................... 293 c.1 register index (in alphabetical order with respect to register name) ........................ 293 c.2 register index (in alphabetical order with respect to register symbol) ..................... 296 appendix d revision history .................................................................................................. 29 9
17 list of figures (1/4) figure no. title page 2-1. i/o circuits of pins ....................................................................................................... ..................... 39 3-1. memory map ( m pd780973(a)) .......................................................................................................... 41 3-2. memory map ( m pd78f0974) ............................................................................................................ 42 3-3. data memory addressing ( m pd780973(a)) ...................................................................................... 45 3-4. data memory addressing ( m pd78f0974) ......................................................................................... 46 3-5. program counter configuration .............................................................................................. .......... 47 3-6. program status word configuration .......................................................................................... ....... 47 3-7. stack pointer configuration ................................................................................................ .............. 49 3-8. data to be saved to stack memory ........................................................................................... ....... 49 3-9. data to be reset from stack memory ......................................................................................... ...... 49 3-10. general register configuration ............................................................................................ ............ 50 4-1. eeprom block diagram ....................................................................................................... ........... 68 4-2. eeprom write control register (eewc) format ........................................................................... 69 5-1. port types ................................................................................................................. ........................ 73 5-2. p00 to p07 block diagram ................................................................................................... ............. 76 5-3. p10 to p14 block diagram ................................................................................................... ............. 76 5-4. p20 to p27 block diagram ................................................................................................... ............. 77 5-5. p30 to p37 block diagram ................................................................................................... ............. 78 5-6. p40 to p44 block diagram ................................................................................................... ............. 79 5-7. p50 to p54 block diagram ................................................................................................... ............. 80 5-8. p60 and p61 block diagram .................................................................................................. ........... 81 5-9. p81 block diagram .......................................................................................................... ................. 82 5-10. p82 to p87 block diagram .................................................................................................. .............. 82 5-11. p90 to p97 block diagram .................................................................................................. .............. 83 5-12. port mode register (pm0, pm4 to pm6, pm8, pm9) format ........................................................... 86 5-13. port mode register (pm2, pm3) format ...................................................................................... .... 86 5-14. pull-up resistor option register (pu0) format ............................................................................. .. 87 6-1. clock generator block diagram .............................................................................................. ......... 89 6-2. processor clock control register (pcc) format ............................................................................. 9 0 6-3. oscillator mode register (oscm) format ..................................................................................... ... 91 6-4. external circuit of main system clock oscillator ........................................................................... ... 92 6-5. incorrect examples of resonator connection ................................................................................. .93 6-6. switching cpu clock ........................................................................................................ ................ 97 7-1. timer 0 (tm0) block diagram ................................................................................................ ........... 101 7-2. 16-bit timer mode control register (tmc0) format ........................................................................ 103 7-3. capture pulse control register (crc0) format .............................................................................. 1 04 7-4. prescaler mode register (prm0) format ...................................................................................... .. 105 7-5. configuration diagram for pulse width measurement by free-running counter ............................ 106 7-6. timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) ................................................................... 106
18 list of figures (2/4) figure no. title page 7-7. cr0m capture operation with rising edge specified ..................................................................... 107 7-8. timing of pulse width measurement operation by free-running counter (with both edges specified) .................................................................................................... .......... 108 7-9. 16-bit timer register start timing ......................................................................................... ........... 109 7-10. capture register data retention timing .................................................................................... ...... 109 8-1. timer 1 (tm1) block diagram ................................................................................................ ........... 111 8-2. timer clock select register 1 (tcl1) format ................................................................................ .. 113 8-3. 8-bit timer mode control register 1 (tmc1) format ....................................................................... 114 8-4. interval timer operation timings ........................................................................................... ........... 115 8-5. timer 1 start timing ....................................................................................................... ................... 118 8-6. timing after compare register change during timer count operation ........................................... 118 9-1. timer 2 (tm2) block diagram ................................................................................................ ........... 119 9-2. timer 3 (tm3) block diagram ................................................................................................ ........... 120 9-3. timer clock select register 2 (tcl2) format ................................................................................ .. 122 9-4. timer clock select register 3 (tcl3) format ................................................................................ .. 123 9-5. 8-bit timer mode control register n (tmcn) format ....................................................................... 124 9-6. interval timer operation timings ........................................................................................... ........... 125 9-7. external event counter operation timings (with rising edge specified) ........................................ 128 9-8. pwm output operation timing ................................................................................................ ......... 130 9-9. timing of operation by change of crn ....................................................................................... ..... 131 9-10. timer n start timing ...................................................................................................... .................... 132 9-11. timing after compare register change during timer count operation ........................................... 132 10-1. watch timer block diagram ................................................................................................. ............ 133 10-2. watch timer mode control register (wtm) format ........................................................................ 135 10-3. operation timing of watch timer/interval timer ............................................................................ ... 137 11-1. watchdog timer block diagram .............................................................................................. ......... 139 11-2. watchdog timer clock select register (wdcs) format .................................................................. 141 11-3. watchdog timer mode register (wdtm) format ............................................................................ 142 12-1. clock output control circuit block diagram ................................................................................ ..... 145 12-2. clock output selection register (cks) format .............................................................................. .. 146 12-3. port mode register 6 (pm6) format ......................................................................................... ........ 147 12-4. remote control output application example ................................................................................. .. 148 13-1. a/d converter block diagram ............................................................................................... ............ 149 13-2. power-fail detection function block diagram ............................................................................... .. 150 13-3. a/d converter mode register (adm1) format ................................................................................. 152 13-4. analog input channel specification register (ads1) format .......................................................... 153 13-5. power-fail compare mode register (pfm) format ......................................................................... 154 13-6. basic operation of 8-bit a/d converter .................................................................................... ........ 156 13-7. relation between analog input voltage and a/d conversion result ................................................ 157
19 list of figures (3/4) figure no. title page 13-8. a/d conversion ............................................................................................................ ..................... 159 13-9. example of method of reducing current consumption in standby mode ....................................... 160 13-10. analog input pin connection .............................................................................................. .............. 161 13-11. a/d conversion end interrupt request generation timing .............................................................. 162 13-12. d/a converter mode register (dam1) format ................................................................................ . 163 14-1. uart block diagram ........................................................................................................ ................ 165 14-2. asynchronous serial interface mode register (asim) format ......................................................... 168 14-3. asynchronous serial interface status register (asis) format ........................................................ 169 14-4. baud rate generator control register (brgc) format .................................................................. 170 14-5. error tolerance (when k = 0) including sampling errors .................................................................. 17 6 14-6. format of transmit/receive data in asynchronous serial interface ................................................ 177 14-7. timing of asynchronous serial interface transmit completion interrupt .......................................... 179 14-8. timing of asynchronous serial interface receive completion interrupt ........................................... 180 14-9. receive error timing ...................................................................................................... .................. 181 15-1. sio3 block diagram ........................................................................................................ ................. 183 15-2. serial operation mode register (csim) format .............................................................................. . 185 15-3. serial operation mode register (csim) format .............................................................................. . 186 15-4. serial operation mode register (csim) format .............................................................................. . 187 15-5. three-wire serial i/o mode timing ......................................................................................... ......... 188 16-1. lcd controller/driver block diagram ....................................................................................... ........ 190 16-2. lcd clock select circuit block diagram .................................................................................... ...... 191 16-3. lcd display mode register (lcdm) format ................................................................................... 192 16-4. lcd display control register (lcdc) format ................................................................................ . 193 16-5. relationship between lcd display data memory contents and segment/common outputs ......... 195 16-6. common signal waveform .................................................................................................... ........... 197 16-7. common signal and segment signal voltages and phases ............................................................ 197 16-8. example of connection of lcd drive power supply ........................................................................ 199 16-9. 4-time-division lcd display pattern and electrode connections ................................................... 200 16-10. 4-time-division lcd panel connection example ............................................................................ 2 01 16-11. 4-time-division lcd drive waveform examples (1/3 bias method) ............................................... 202 16-12. lcd timer control register (lcdtm) format ................................................................................ . 203 17-1. sound generator block diagram ............................................................................................. ......... 205 17-2. concept of each signal .................................................................................................... ................ 206 17-3. sound generator control register (sgcr) format ......................................................................... 208 17-4. sound generator buzzer control register (sgbr) format ............................................................. 210 17-5. sound generator amplitude register (sgam) format ..................................................................... 211 17-6. sound generator output operation timing ................................................................................... ... 212 17-7. sound generator output operation timing ................................................................................... ... 212
20 list of figures (4/4) figure no. title page 18-1. meter controller/driver block diagram ..................................................................................... ........ 213 18-2. 1-bit addition circuit block diagram ...................................................................................... ........... 214 18-3. timer mode control register (mcntc) format ............................................................................... 2 16 18-4. compare control register n (mcmpcn) format .............................................................................. 21 7 18-5. port mode control register (pmc) format ................................................................................... ... 218 18-6. restart timing after count stop (count start ? count stop ? count start) ...................................... 220 18-7. timing in 1-bit addition circuit operation ................................................................................ ......... 221 18-8. timing of output with 1 clock shifted ..................................................................................... .......... 222 19-1. basic configuration of interrupt function ................................................................................. ........ 225 19-2. interrupt request flag register (if0l, if0h, if1l) format .............................................................. 228 19-3. interrupt mask flag register (mk0l, mk0h, mk1l) format ............................................................ 229 19-4. priority specify flag register (pr0l, pr0h, pr1l) format ............................................................ 230 19-5. external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) format ....................................................... 231 19-6. prescaler mode register (prm0) format ..................................................................................... ... 232 19-7. program status word format ................................................................................................ ........... 233 19-8. non-maskable interrupt request generation to acknowledge flowchart ........................................ 235 19-9. non-maskable interrupt request acknowledge timing .................................................................... 235 19-10. non-maskable interrupt request acknowledge operation ............................................................... 236 19-11. interrupt request acknowledge processing algorithm ..................................................................... 23 8 19-12. interrupt request acknowledge timing (minimum time) ................................................................. 239 19-13. interrupt request acknowledge timing (maximum time) ................................................................ 239 19-14. multiple interrupt examples .............................................................................................. ................ 241 19-15. interrupt request hold ................................................................................................... ................... 243 20-1. oscillation stabilization time select register (osts) format ......................................................... 246 20-2. halt mode clear upon interrupt generation ................................................................................. .. 248 20-3. halt mode clear upon reset input .......................................................................................... .... 249 20-4. stop mode clear upon interrupt generation ................................................................................. . 251 20-5. stop mode clear upon reset input .......................................................................................... .... 252 21-1. reset function block diagram .............................................................................................. ........... 253 21-2. timing of reset by reset input ............................................................................................ .......... 254 21-3. timing of reset due to watchdog timer overflow ........................................................................... 2 54 21-4. timing of reset in stop mode by reset input .............................................................................. 2 54 22-1. memory size switching register (ims) format ............................................................................... . 258 22-2. transmission method selection format ...................................................................................... ..... 259 22-3. flashpro ii connection using 3-wire serial i/o method ................................................................... 26 0 22-4. flashpro ii connection using uart method .................................................................................. .. 261 22-5. flashpro ii connection using pseudo 3-wire serial i/o method ...................................................... 261 a-1. development tool configuration ............................................................................................. .......... 280 a-2. dimensions of tgf-080rap (reference) ....................................................................................... . 289
21 list of tables (1/2) table no. title page 2-1. pin input/output circuit types ............................................................................................. ............. 38 3-1. internal memory capacity ................................................................................................... .............. 43 3-2. vector table ............................................................................................................... ....................... 43 3-3. internal high-speed ram capacity ........................................................................................... ....... 44 3-4. internal high-speed ram area ............................................................................................... ......... 48 3-5. special function register list ............................................................................................. ............. 52 5-1. port functions ............................................................................................................. ...................... 74 5-2. port configuration ......................................................................................................... .................... 75 5-3. port mode register and output latch settings when using alternate functions ............................. 85 6-1. clock generator configuration .............................................................................................. ........... 89 6-2. relation between cpu clock and minimum instruction execution time .......................................... 90 6-3. maximum time required for switching cpu clock .......................................................................... 96 7-1. timer/event counter operations ............................................................................................. ......... 100 7-2. timer 0 configuration ...................................................................................................... ................. 102 8-1. timer 1 configuration ...................................................................................................... ................. 112 9-1. timers 2 and 3 configurations .............................................................................................. ............ 121 10-1. interval timer interval time .............................................................................................. ................ 134 10-2. watch timer configuration ................................................................................................. .............. 134 10-3. interval timer interval time .............................................................................................. ................ 136 11-1. watchdog timer runaway detection time ..................................................................................... .. 140 11-2. interval time ............................................................................................................. ........................ 140 11-3. watchdog timer configuration .............................................................................................. ........... 141 11-4. watchdog timer runaway detection time ..................................................................................... .. 143 11-5. interval timer interval time .............................................................................................. ................ 144 12-1. clock output control circuit configuration ................................................................................ ....... 145 13-1. a/d converter configuration ............................................................................................... .............. 150 14-1. uart configuration ........................................................................................................ .................. 166 14-2. relation between 5-bit counters source clock and n value ......................................................... 175 14-3. relation between main system clock and baud rate ..................................................................... 176 14-4. causes of receive errors .................................................................................................. ............... 181 15-1. sio3 configuration ........................................................................................................ ................... 184
22 list of tables (2/2) table no. title page 16-1. maximum number of display pixels .......................................................................................... ....... 189 16-2. lcd controller/driver configuration ....................................................................................... .......... 190 16-3. com signals ............................................................................................................... ...................... 196 16-4. lcd drive voltage ......................................................................................................... ................... 196 16-5. lcd drive voltage ......................................................................................................... ................... 198 16-6. selection and non-selection voltages (com0 to com3) ................................................................ 200 17-1. sound generator configuration ............................................................................................. ........... 206 18-1. meter controller/driver configuration ..................................................................................... .......... 214 19-1. interrupt source list ..................................................................................................... .................... 224 19-2. flags corresponding to interrupt request sources ......................................................................... 2 27 19-3. times from generation of maskable interrupt request until servicing ............................................. 237 19-4. interrupt request enabled for multiple interrupt during interrupt servicing ...................................... 240 20-1. halt mode operating status ................................................................................................ ........... 247 20-2. operation after halt mode clear ........................................................................................... ......... 249 20-3. stop mode operating status ................................................................................................ .......... 250 20-4. operation after stop mode clear ........................................................................................... ......... 252 21-1. hardware status after reset ............................................................................................... ............. 255 22-1. differences between m pd78f0974 and m pd780973(a) ................................................................... 257 22-2. memory size switching register settings ................................................................................... ..... 258 22-3. transmission method list .................................................................................................. ............... 259 22-4. main functions of flash memory programming ............................................................................... 2 60 23-1. operand identifiers and description formats ............................................................................... .... 264 a-1. upgrading former in-circuit emulator for 78k/0 series to ie-78001-r-a ......................................... 288
23 chapter 1 outline 1.1 features ? internal memory item program memory data memory part number (rom/flash memory) internal high-speed ram lcd display ram eeprom tm m pd780973(a) 24 kbytes 768 bytes 20 4 bits 256 bytes m pd78f0974 32 kbytes 1024 bytes ? high-speed instruction execution time (0.24 m s: @ 8.38-mhz operation with main system clock) ? instruction set suited to system control ? bit manipulation possible in all address spaces ? multiply and divide instructions ? fifty-six i/o ports : (including pins that have an alternate function as segment signal output) ? lcd controller/driver ? segment signal output : 20 max. ? common signal output : 4 max. ? bias : 1/3 bias ? power supply voltage : v lcd = 3.0 v to v dd ? 8-bit resolution a/d converter : 5 channels ? serial interface : 2 channels ? 3-wire serial i/o mode : 1 channel ? uart mode : 1 channel ? timer : six channels ? 16-bit timer : 1 channel ? 8-bit timer : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel ? meter controller/driver : pwm output (8-bit resolution) : 16 : can set pulse width with a precision of 8 + 1 bits with 1-bit addition function ? sound generator : 1 channel ? vectored interrupt sources : 21 ? power supply voltage : v dd = 5 v 10% 1.2 applications automobile meter (dash board) control
24 chapter 1 outline 1.3 ordering information part number package internal rom m pd780973gf(a)- -3b9 80-pin plastic qfp (14 20 mm) mask rom m pd78f0974gf-3b9 80-pin plastic qfp (14 20 mm) flash memory 1.4 quality grade part number package quality grade m pd78f0974gf-3b9 80-pin plastic qfp (14 20 mm) standard m pd780973gf(a)- -3b9 80-pin plastic qfp (14 20 mm) special remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
25 chapter 1 outline 1.5 pin configuration (top view) 80-pin plastic qfp (14 20 mm) m pd780973gf(a)- , 78f0974gf 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 com0 v lcd smv ss smv dd sm11/p20 sm12/p21 sm13/p22 sm14/p23 sm21/p24 sm22/p25 sm23/p26 sm24/p27 sm31/p30 sm32/p31 sm33/p32 sm34/p33 sm41/p34 sm42/p35 sm43/p36 sm44/p37 smv dd smv ss sgo/sgof/p61 sgoa/pcl/p60 p87/s13 p86/s14 p85/s15 p84/s16 p83/s17 p82/s18 tpo/p81/s19 ic (v pp ) x1 x2 v ss v dd reset p07 p06 p05 p04 p03 intp2/p02 intp1/p01 intp0/p00 av ref p14/ani4 p13/ani3 ani2/p12 ani1/p11 ani0/p10 av ss sck/p50 so/p51 si/p52 v dd v ss rxd/p53 txd/p54 ti00/p40 ti01/p41 ti02/p42 tio2/p43 tio3/p44 s12/p90 s11/p91 s10/p92 s9/p93 s8/p94 s7/p95 s6/p96 s5/p97 s4 s3 s2 s1 s0 com3 com2 com1 cautions 1. connect ic (internally connected) pin to v ss directly. 2. connect av ss pin to v ss . remarks 1. when these devices are used in applications that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to the two v dd individually, and connecting the two v ss to different ground lines, is recommended. 2. pin connection in parentheses is intended for the m pd78f0974.
26 chapter 1 outline ani0 to ani4 : analog input sck : serial clock av ref : analog reference voltage sgo : sound generator output av ss : analog ground sgoa : sound generator amplitude output com0 to com3 : common output sgof : sound generator frequency output ic : internally connected si : serial input intp0 to intp2 : interrupt from peripherals sm11 to sm14, sm21 to sm24, sm31 to sm34, sm41 to sm44 p00 to p07 : port0 : meter output p10 to p14 : port1 smv dd : meter controller power supply p20 to p27 : port2 smv ss : meter controller ground p30 to p37 : port3 so : serial output p40 to p44 : port4 ti00 to ti02 : timer input p50 to p54 : port5 tio2, tio3 : timer output/event counter input p60, p61 : port6 tpo : prescaler output p81 to p87 : port8 txd : transmit data p90 to p97 : port9 v dd : power supply pcl : clock output v lcd : lcd power supply reset : reset v pp : programming power supply rxd : receive data v ss : ground s0 to s19 : segment output x1, x2 : crystal (main system clock)
27 chapter 1 outline 1.6 78k/0 series product development these products are a further development in the 78k/0 series. the designations appearing inside the boxes are subseries names. note under planning pd78014 pd78002 pd78083 pd78002y 100-pin 100-pin 100-pin 64-pin 64-pin 64-pin 42/44-pin control y subseries products are compatible with i 2 c bus. timer was added to the pd78054, and the external interface function was enhanced. emi-noise reduced version of the pd78078. rom-less versions of the pd78078. a/d converter and 16-bit timer were added to the pd78002. a/d converter was added to the pd78002. basic subseries for control. on-chip uart, capable of operating at a low voltage (1.8 v). pd780018ay 100-pin serial i/o of the pd78078y was enhanced, and only selected functions are provided. pd78078 pd78070a pd78075b pd78070ay m m mm m mm m mm m m m m m m inverter control pd780964 64-pin m a/d converter of the pd780924 was enhanced. pd78078y m pd78018f pd780001 pd78018fy pd78014y 80-pin 80-pin 64-pin 78k/0 series products in mass production products under development emi-noise reduced version of the pd78054. uart and d/a converter were added to the pd78014, and i/o was enhanced. low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities available. a/d converter of the pd780024 was enhanced. emi-noise reduced version of the pd78018f. on-chip inverter control circuit and uart, emi-noise reduced version. serial i/o of the pd78018f was enhanced. serial i/o of the pd78054 was enhanced, emi-noise reduced version. pd780058 80-pin m mm pd780034 pd780024 pd78014h pd780034y pd780024y 64-pin 64-pin 64-pin mm mm m m m m m m m m m fip tm drive pd78044f 100-pin 80-pin 80-pin m m i/o and fip c/d of the pd78044f were enhanced, display output total: 53 i/o and fip c/d of the pd78044h were enhanced, display output total: 48 n-ch open-drain input/output was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 m m 100-pin pd780924 64-pin m pd780308 pd78064b pd78064 100-pin 100-pin 100-pin m m sio of the pd78064 was enhanced, and rom and ram were expanded. emi-noise reduced version of the pd78064. basic subseries for driving lcds, on-chip uart. m pd780308y m pd78064y m lcd drive m m pd78054 m pd78054y m pd78058fy m pd780058y note m pd78058f m pd78044h m m pd780228 pd780208 m m m iebus tm supported pd78098b 80-pin m emi-noise reduced version of the pd78098. iebus controller was added to the pd78054. pd78098 80-pin m m meter control pd780973 80-pin m on-chip automobile meter driving controller/driver. pd780988 64-pin m m inverter control, timer, and sio of the pd780964 were enhanced, with rom and ram expansion.
28 chapter 1 outline the major functional differences among the subseries are shown below. function rom timer 8-bit 10-bit 8-bit v dd external serial interface i/o min. subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch C 2 ch 3 ch (uart: 1 ch) 88 1.8 v available m pd78078 48 k to 60 k m pd78070a C 61 2.7 v m pd780058 24 k to 60 k 2 ch 3 ch (time-division 68 1.8 v uart: 1ch) m pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780034 8 k to 32 k C8 chC 3 ch (uart: 1 ch, time- 51 1.8 v m pd780024 8 ch C division 3-wire: 1 ch) m pd78014h 2 ch 53 m pd78018f 8 k to 60 k m pd78014 8 k to 32 k 2.7 v m pd780001 8 k C C 1 ch 39 C m pd78002 8 k to 16 k 1 ch C 53 available m pd78083 C 8 ch 1 ch (uart: 1 ch) 33 1.8 v C inverter m pd780988 32 k to 60 k 3 ch note 1 C 1 ch C 8 ch C 3 ch (uart: 2 ch) 47 4.0 v available control m pd780964 8 k to 32 k note 2 2 ch (uart: 2 ch) 2.7 v m pd780924 8 ch C fip m pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch C C 2 ch 74 2.7 v C drive m pd780228 48 k to 60 k 3 ch C C 1 ch 72 4.5 v m pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 68 2.7 v m pd78044f 16 k to 40 k 2 ch lcd m pd780308 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch C C 3 ch (time-division 57 2.0 v C drive uart: 1 ch) m pd78064b 32 k 2 ch (uart: 1 ch) m pd78064 16 k to 32 k iebus m pd78098b 40 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch C 2 ch 3 ch (uart: 1 ch) 69 2.7 v available supported m pd78098 32 k to 60 k meter m pd780973 24 k to 32 k 3 ch 1 ch 1 ch 1 ch 5 ch C C 2 ch (uart: 1 ch) 56 4.5 v C control notes 1. 16-bit timer: 2 channels 10-bit timer: 1 channel 2. 10-bit timer: 1 channel
29 chapter 1 outline 1.7 block diagram remarks 1. the internal rom and ram capacities depend on the product. 2. memory type in parentheses is for the m pd78f0974. ti00/p40 to ti02/p42 16-bit timer0 port0 p00 to p07 p10 to p14 p20 to p27 p30 to p37 p40 to p44 p50 to p54 p60, p61 p81 to p87 p90 to p97 s0 to s4 s5/p97 to s12/p90 port1 port2 port3 port4 port5 port6 port8 port9 lcd controller/ driver meter controller/ driver system control 8-bit timer1 8-bit timer/ event counter2 8-bit timer/ event counter3 watchdog timer serial interface a/d converter interrupt control standby control sound generator output v dd v ss ic (v pp ) clock output control power fail detector uart ram 78k/0 cpu core rom flash memory eeprom watch timer tio2/p43 tio3/p44 sck/p50 so/p51 si/p52 ani0/p10 to ani4/p14 av ss av ref rxd/p53 txd/p54 intp0/p00 to intp2/p02 pcl/sgoa/p60 sgo/sgof/p61 s13/p87 to s18/p82 sm11/p20 to sm14/p23 sm21/p24 to sm24/p27 sm31/p30 to sm34/p33 sm41/p34 to sm44/p37 s19/p81/tpo com0 to com3 v lcd smv dd smv ss x1 x2 reset
30 chapter 1 outline 1.8 outline of function part number item m pd780973(a) m pd78f0974 internal memory rom 24 kbytes 32 kbytes (mask rom) (flash memory) internal high-speed ram 768 bytes 1024 bytes eeprom 256 bytes lcd display ram 20 4 bits general register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.24 m s/0.48 m s/0.95 m s/1.91 m s/3.81 m s (in operation at 8.38 mhz) instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, and boolean operation) i/o port total : 56 (including pins shared with segment ? cmos input : 5 signal output) ? cmos output : 16 ? cmos input/output : 35 a/d converter ? 8-bit resolution 5 channels ? power-fail detection function lcd controller/driver ? segment signal outputs : 20 max. ? common signal outputs : 4 max. ? bias : 1/3 bias only serial interface ? 3-wire serial i/o mode : 1 channel ? uart mode : 1 channel timer ? 16-bit timer : 1 channel ? 8-bit timer : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel meter control pwm output (8-bit resolution) : 16 can set pulse width with a precision of 8 + 1 bits with 1-bit addition function sound generator 1 channel clock output 65.5 khz, 131 khz, 262 khz, 524 khz, 1.04 mhz, 2.09 mhz, 4.19 mhz, 8.38 mhz (@ 8.38-mhz operation with main system clock) vectored interrupt maskable internal: 16, external: 3 source non-maskable internal: 1 software 1 power supply voltage v dd (smv dd ) = 5 v 10% operating ambient temperature t a = C40 to +85?c package 80-pin plastic qfp (14 20 mm)
31 chapter 2 pin function 2.1 pin function list (1) port pins pin name input/output function after reset alternate function p00 to p02 input/output input intp0 to intp2 p03 to p07 p10 to p14 input port 1 input ani0 to ani4 5-bit input only port. p20 to p23 output port 2 hi-z sm11 to sm14 p24 to p27 8-bit output only port. sm21 to sm24 p30 to p33 output port 3 hi-z sm31 to sm34 p34 to p37 8-bit output only port. sm41 to sm44 p40 to p42 input/output input ti00 to ti02 p43, p44 tio2, tio3 p50 input/output port 5 input sck p51 5-bit input/output port. so p52 input/output mode can be specified bit-wise. si p53 rxd p54 txd p60 input/output input pcl/sgoa p61 sgo/sgof p81 input/output input s19/tpo p82 to p87 s18 to s13 p90 to p97 input/output port 9 input s12 to s5 8-bit input/output port. input/output mode can be specified bit-wise. can be set in i/o port mode or segment output mode in 2- bit units by using lcd display control register (lcdc). port 0 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 4 5-bit input/output port. input/output mode can be specified bit-wise. port 6 2-bit input/output port. input/output mode can be specified bit-wise. port 8 7-bit input/output port. input/output mode can be specified bit-wise. can be set in i/o port mode or segment output mode in 2- bit units by using lcd display control register (lcdc).
32 chapter 2 pin function (2) non-port pins pin name input/output function after reset alternate function intp0 to intp2 input external interrupt request input with specifiable valid edges input p00 to p02 (rising edge, falling edge, both rising and falling edges). si input serial interface serial data input. input p52 so output serial interface serial data output. input p51 sck input/output serial interface serial data input/output. input p50 rxd input asynchronous serial interface serial data input. input p53 txd output asynchronous serial interface serial data output. input p54 ti00 input capture trigger signal input to capture register (cr00). input p40 ti01 capture trigger signal input to capture register (cr01). p41 ti02 capture trigger signal input to capture register (cr02). p42 tio2 input/output 8-bit timer (tm2) input/output. input p43 tio3 8-bit timer (tm3) input/output. p44 pcl output clock output (for main system clock trimming). input sgoa/p60 sgoa output sound generator signal output. input pcl/p60 sgof sgo/p61 sgo sgof/p61 tpo output prescaler output of 16-bit timer (tm0). input p81/s19 s0 to s4 output segment signal output of lcd controller/driver. output s5 to s12 input p97 to p90 s13 to s18 p87 to p82 s19 p81/tpo com0 to com3 output common signal output of lcd controller/driver. output v lcd lcd driving power supply. sm11 to sm14 output meter control signal output. hi-z p20 to p23 sm21 to sm24 p24 to p27 sm31 to sm34 p30 to p33 sm41 to sm44 p34 to p37 ani0 to ani4 input a/d converter analog input. input p10 to p14 av ref input a/d converter reference voltage input (shared with analog power supply). av ss a/d converter ground potential. same potential as v ss . reset input system reset input. x1 input crystal connection for main system clock oscillation. x2 smv dd power supply for meter controller/driver. smv ss ground potential for meter controller/driver. v dd positive power supply. v ss ground potential. v pp high-voltage application for program write/verify. connect directly to v ss in normal operating mode. ic internally connected. connect directly to v ss .
33 chapter 2 pin function 2.2 description of pin functions 2.2.1 p00 to p07 (port 0) these pins constitute an 8-bit input/output port. in addition, they are also used to input external interrupt request signals. the following operating modes can be specified bit-wise. (1) port mode in this mode, p00 to p07 function as an 8-bit input/output port. p00 to p07 can be specified as an input or output port bit-wise with port mode register 0 (pm0). when these pins are used as an input port, an on-chip pull-up resistor can be used if so specified by the pull-up resistor option register (pu0). (2) control mode in this mode, p00 to p07 function as external interrupt input pins (intp0 to intp2) and external interrupt request input pins with specifiable valid edges (rising edge, falling edge, both rising and falling edges). 2.2.2 p10 to p14 (port 1) these pins constitute a 5-bit input only port. in addition, they are also used to input a/d converter analog signals. the following operating modes can be specified bit-wise. (1) port mode in this mode, p10 to p14 function as a 5-bit input only port. (2) control mode in this mode, p10 to p14 function as a/d converter analog input pins (ani0 to ani4). 2.2.3 p20 to p27 (port 2) these pins constitute an 8-bit output only port. in addition, they are also used as pwm output pins to control meters. the following operating modes can be specified bit-wise. (1) port mode in this mode, p20 to p27 function as an 8-bit output only port. they go into a high-impedance state when 1 is set to port mode register 2 (pm2). (2) control mode in this mode, p20 to p27 function as pwm output pins (sm11 to sm14 and sm21 to sm24) for meter control.
34 chapter 2 pin function 2.2.4 p30 to p37 (port 3) these pins constitute an 8-bit output only port. in addition, they also function as pwm output pins to control meters. the following operating modes can be specified bit-wise. (1) port mode in this mode, p30 to p37 function as an 8-bit output only port. they go into a high-impedance state when 1 is set to port mode register 3 (pm3). (2) control mode in this mode, p30 to p37 function as pwm output pins (sm31 to sm34 and sm41 to sm44) for meter control. 2.2.5 p40 to p44 (port 4) these pins constitute a 5-bit input/output port. in addition, they also function as timer input/output pins. the following operating modes can be specified bit-wise. (1) port mode in this mode, p40 to p44 function as a 5-bit input/output port. they can be set bit-wise in the input or output mode by using port mode register 4 (pm4). (2) control mode in this mode, p40 to p44 function as timer input/output pins. (a) tio2, tio3 timer output pins. (b) ti00 to ti02 these pins input a capture trigger signal to the 16-bit timer capture registers (cr00 to cr02). 2.2.6 p50 to p54 (port 5) these pins constitute a 5-bit input/output port. in addition, they also function as serial interface data input/output and clock input/output pins. the following operating modes can be specified bit-wise. (1) port mode in this mode, p50 to p54 function as a 5-bit input/output port. they can be set bit-wise in the input or output mode by using port mode register 5 (pm5). (2) control mode in this mode, p50 to p54 function as serial interface data input/output and clock input/output. (a) si serial interface serial data input pin. (b) so serial interface serial data output pin.
35 chapter 2 pin function (c) sck serial interface serial clock input/output pin. (d) rxd, txd asynchronous serial interface serial data input/output pins. 2.2.7 p60, p61 (port 6) these pins constitute a 2-bit input/output port. in addition, they also function as clock output and sound generator output pins. the following operating modes can be specified bit-wise. (1) port mode in this mode, p60 and p61 function as a 2-bit input/output port. they can be set bit-wise in the input or output mode by using port mode register 6 (pm6). (2) control mode in this mode, p60 and p61 function as clock output and sound generator output pins. (a) pcl clock output pin. (b) sgof sound generator (without amplitude) signal output pin. (c) sgo sound generator (with amplitude) signal output pin. (d) sgoa sound generator amplitude signal output pin. 2.2.8 p81 to p87 (port 8) these pins constitute a 7-bit input/output port. in addition, they also function as output pins for segment signals from the internal lcd controller/driver, and one of them as a prescaler signal output pin. the following operating modes can be specified bit-wise. (1) port mode in this mode, p81 to p87 function as a 7-bit input/output port. they can be set bit-wise in the input or output mode by using port mode register 8 (pm8). (2) control mode in this mode, p81 to p87 function as segment signal output pins of the lcd controller/driver, and one of them as a prescaler signal output pins. (a) s13 to s19 segment signal output pins of the lcd controller/driver. (b) tpo prescaler signal output pin of the 16-bit timer.
36 chapter 2 pin function 2.2.9 p90 to p97 (port 9) these pins constitute an 8-bit input/output port. in addition, they also function to output segment signals from the internal lcd controller/driver. the following operating modes can be specified bit-wise. (1) port mode in this mode, p90 to p97 function as an 8-bit input/output port. they can be set bit-wise in the input or output mode by using port mode register 9 (pm9). (2) control mode in this mode, p90 to p97 function as segment signal output pins (s5 to s12) of the lcd controller/driver. 2.2.10 com0 to com3 these pins output common signals from the internal lcd controller/driver during 4-time division drive in 1/3 bias mode (com0 to com3 outputs). 2.2.11 v lcd this pin supplies a voltage to drive an lcd. 2.2.12 av ref this is an a/d converter reference voltage input pin. this pin also functions as an analog power supply pin. supply power to this pin when the a/d converter is used. when a/d converter is not used, connect this pin to v ss . 2.2.13 av ss this is a ground voltage pin of a/d converter. always use the same voltage as that of the v ss pin even when an a/d converter is not used. 2.2.14 reset this is a low-level active system reset input pin. 2.2.15 x1 and x2 crystal resonator connect pins for main system clock oscillation. when using an external clock supply, input it to x1 and its inverted signal to x2. 2.2.16 smv dd this pin supplies a positive power to the meter controller/driver. 2.2.17 smv ss this is the ground pin of the meter controller/driver. 2.2.18 v dd positive power supply port pin. 2.2.19 v ss ground potential port pin.
37 chapter 2 pin function 2.2.20 v pp ( m pd78f0974) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. directly connect this pin to v ss in the normal operating mode. 2.2.21 ic ( m pd780973(a)) the ic (internally connected) pin is provided to set the test mode to check the m pd780973(a) before shipment. in the normal operating mode, directly connect this pin to the v ss pin with as short a wiring length as possible. when a potential difference is generated between the ic pin and v ss pin because the wiring between those two pins is too long or external noise is input to the ic pin, the user's program may not run normally. ? directly connect the ic pin to the v ss pin. keep short ic v ss
38 chapter 2 pin function 2.3 input/output circuits and recommended connection of unused pins table 2-1 shows the input/output circuit types of pins and the recommended connection for unused pins. refer to figure 2-1 for the configuration of the input/output circuit of each type. table 2-1. pin input/output circuit types pin name input/output circuit type input/output recommended connection of unused pins p00/intp0 8-a input/output independently connect to v ss via a resistor. p01/intp1 p02/intp2 p03 to p07 p10/ani0 to p14/ani4 9 input independently connect to v dd or v ss via a resistor. p20/sm11 to p23/sm14 4 output leave open. p24/sm21 to p27/sm24 p30/sm31 to p33/sm34 p34/sm41 to p37/sm44 p40/ti00 to p42/ti02 8 input/output independently connect to v dd or v ss via a resistor. p43/tio2 p44/tio3 p50/sck p51/so 5 p52/si 8 p53/rxd p54/txd 5 p60/sgoa/pcl p61/sgo/sgof p81/s19/tpo 17-g p82/s18 to p87/s13 p90/s12 to p97/s5 s0 to s4 17 output leave open. com0 to com3 18 v lcd reset 2 input smv dd connect to v dd . smv ss connect to v ss . av ref av ss v pp ( m pd78f0974) ic ( m pd780973(a)) connect directly to v ss .
39 chapter 2 pin function figure 2-1. i/o circuits of pins (1/2) type 2 schmitt-triggered input with hysteresis characteristics in type 5 data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable type 4 data output disable p-ch out v dd n-ch type 8-a type 8 type 9 data output disable p-ch in/out v dd n-ch data output disable input enable p-ch in/out v dd n-ch + e input enable comparator p-ch n-ch v ref (threshold voltage) in push-pull output whose output can go into a high- impedance state (both p-ch and n-ch are off).
40 chapter 2 pin function figure 2-1. i/o circuits of pins (2/2) type 17 type 18 type 17-g v lc0 v lc1 seg data v lc2 p-ch n-ch p-ch n-ch p-ch n-ch out v lc0 v lc1 com data v lc2 p-ch n-ch p-ch n-ch p-ch n-ch out n-ch p-ch v lc0 v lc1 seg data v lc2 p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch input enable output disable data in/out v dd
41 chapter 3 cpu architecture 3.1 memory spaces the m pd780973 subseries can access a 64-kbyte memory space. figures 3-1 and 3-2 show memory maps of the respective devices. figure 3-1. memory map ( m pd780973(a)) 0000h data memory space general registers 32 8 bits internal rom 24576 8 bits 5fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area lcd display ram 20 4 bits reserved program memory space 6000h 5fffh fa59h fa58h fa6dh fa6ch fee0h fedfh ff00h feffh ffffh internal high-speed ram 768 8 bits special function registers (sfrs) 256 8 bits reserved fc00h fbffh reserved eeprom 256 8 bits fa00h f9ffh f900h f8ffh
42 chapter 3 cpu architecture figure 3-2. memory map ( m pd78f0974) 0000h data memory space general registers 32 8 bits flash memory 32768 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area lcd display ram 20 4 bits reserved program memory space 8000h 7fffh fa59h fa58h fa6dh fa6ch fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh reserved eeprom 256 8 bits fa00h f9ffh f900h f8ffh
43 chapter 3 cpu architecture 3.1.1 internal program memory space the internal program memory space contains the program and table data. normally, it is addressed with the program counter (pc). the m pd780973 subseries incorporate internal rom (or flash memory), as listed below. table 3-1. internal memory capacity part number type capacity m pd780973(a) mask rom 24576 8 bits (0000h to 5fffh) m pd78f0974 flash memory 32768 8 bits (0000h to 7fffh) the following three areas are allocated to the program memory space. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. this area stores program start addresses to which execution branches when the reset signal is input or when an interrupt request is generated. of a 16-bit address, the lower 8 bits are stored at an even address and the higher 8 bits are stored at an odd address. table 3-2. vector table vector table address interrupt source 0000h reset input 0004h intwdt 0006h intad 0008h intovf 000ah inttm00 000ch inttm01 000eh inttm02 0010h intp0 0012h intp1 0014h intp2 0016h intcs10 0018h intser 001ah intsr 001ch intst 001eh inttm1 0020h inttm2 0022h inttm3 0024h intwe 0026h intwi 0028h intwt 003eh brk
44 chapter 3 cpu architecture (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 3.1.2 internal data memory space the m pd780973 subseries have the following ram. (1) internal high-speed ram table 3-3. internal high-speed ram capacity product internal high-speed ram m pd780973(a) 768 8 bits (fc00h to feffh) m pd78f0974 1024 8 bits (fb00h to feffh) the 32-byte area fee0h to feffh is allocated with four general-purpose register banks composed of eight 8- bit registers. the internal high-speed ram can be used as stack memory. (2) lcd display ram an lcd display ram is allocated to a 20 4 bits area consisting of fa59h to fa6ch. the lcd display ram can also be used as a normal ram. 3.1.3 special function register (sfr) area an on-chip peripheral hardware special-function register (sfr) is allocated in the area ff00h to ffffh (refer to 3.2.3 special function registers (sfrs) table 3-5 special function register list ). caution do not access addresses where the sfr is not assigned.
45 chapter 3 cpu architecture 3.1.4 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. the address of an instruction to be executed next is addressed by the program counter (pc) (for details, see 3.3 instruction address addressing ). several addressing modes are provided for addressing the memory relevant to the execution of instructions for the m pd780973 subseries, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general- purpose registers are available for use. data memory addressing is illustrated in figures 3-3 and 3-4. for the details of each addressing mode, see 3.4 operand address addressing . figure 3-3. data memory addressing ( m pd780973(a)) 0000h general registers 32 8 bits internal rom 24576 8 bits lcd display ram 20 4 bits eeprom 256 8 bits 6000h 5fffh fa59h fa58h fa6dh fa6ch fee0h fedfh ff00h feffh ffffh internal high-speed ram 768 8 bits reserved fc00h fbffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing fa00h f9ffh reserved f900h f8ffh reserved
46 chapter 3 cpu architecture figure 3-4. data memory addressing ( m pd78f0974) 0000h general registers 32 8 bits flash memory 32768 8 bits lcd display ram 20 4 bits 8000h 7fffh fa59h fa58h fa6dh fa6ch fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing fa00h f9ffh reserved f900h f8ffh reserved eeprom 256 8 bits
47 chapter 3 cpu architecture 3.2 processor registers the m pd780973 subseries incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, status, and stack memory. the control registers consist of a program counter, a program status word, and a stack pointer. (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-5. program counter configuration pc 15 0 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-6. program status word configuration 70 ie z rbs1 ac rbs0 0 isp cy psw
48 chapter 3 cpu architecture (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie is set to di, and only non-maskable interrupt request becomes acknowledgeable. other interrupt requests are all disabled. when 1, the ie is set to ei and interrupt request acknowledge enable is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources and a priority specify flag. the ie is reset (to 0) upon di instruction execution or interrupt acknowledgement and is set (to 1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (to 1). it is reset (to 0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (to 1). it is reset (to 0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when this flag is 0, low- level vectored interrupts specified with a priority specify flag register (pr0l, pr0h, pr1l) (refer to 19.3 (3) priority specify flag registers (pr0l, pr0h, pr1l) ) are disabled for acknowledgement. actual acknowledgement is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. the internal high-speed ram areas of each product are as follows. table 3-4. internal high-speed ram area product internal high-speed ram area m pd780973(a) fc00h to feffh m pd78f0974 fb00h to feffh
49 chapter 3 cpu architecture figure 3-7. stack pointer configuration figure 3-9. data to be reset from stack memory the sp is decremented prior to write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores data as shown in figures 3-8 and 3-9. caution since reset input makes sp contents undefined, be sure to initialize the sp before instruction execution. figure 3-8. data to be saved to stack memory sp 15 0 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 interrupt and brk instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair, low sp sp _ 2 sp _ 2 register pair, high call, callf, and callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti and retb instructions psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair, low sp sp + 2 sp register pair, high ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3
50 chapter 3 cpu architecture 3.2.2 general registers general registers are mapped at particular addresses (fee0h to feffh) of the data memory. four banks of general registers, each consisting of eight 8-bit registers (x, a, c, b, e, d, l and h) are available. each register can also be used as an 8-bit register. two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupt processing for each bank. figure 3-10. general register configuration (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h
51 chapter 3 cpu architecture 3.2.3 special function registers (sfrs) unlike the general registers, these registers have special functions. they are allocated in the ff00h to ffffh area. the special-function registers can be manipulated like the general registers, with the operation, transfer and bit manipulation instructions. the bit units (1, 8, or 16 bits) for the manipulation vary for each register. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 3-5 gives a list of special-function registers. the meaning of items in the table is as follows. ? symbol symbol indicating the address of a special function register. it is a reserved word in the ra78k/0, and is defined via the header file sfrbit.h in the cc78k/0. it can be described as an instruction operand when the ra78k/ 0 and id78k0 are used. ? r/w indicates whether the corresponding special-function register can be read or written. r/w : read/write enable r : read only w : write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset input.
52 chapter 3 cpu architecture address special-function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff00h port 0 p0 r/w 00h ff01h port 1 p1 r ff02h port 2 p2 r/w note ff03h port 3 p3 ff04h port 4 p4 r/w ff05h port 5 p5 ff06h port 6 p6 ff08h port 8 p8 ff09h port 9 p9 ff0ah 8-bit compare register 1 cr1 ff0bh 8-bit compare register 2 cr2 ff0ch 8-bit compare register 3 cr3 ff0dh 8-bit counter 1 tm1 r ff0eh 8-bit counter 2 tm2 ff0fh 8-bit counter 3 tm3 ff10h capture register 00 cr00 0000h ff11h ff12h capture register 01 cr01 ff13h ff14h capture register 02 cr02 ff15h ff16h 16-bit timer register tm0 ff17h ff18h serial i/o shift register sio r/w 00h ff19h transmit shift register txs w ffh receive buffer register rxb r ffh ff1bh a/d conversion result register adcr1 r 00h note when pm2 and pm3 are set to 00h, read operation is enabled. moreover, when pm2 and pm3 are set to ffh, these ports go into a high-impedance state. table 3-5. special function register list (1/3)
53 chapter 3 cpu architecture address special-function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff20h port mode register 0 pm0 r/w ffh ff22h port mode register 2 pm2 ff23h port mode register 3 pm3 ff24h port mode register 4 pm4 ff25h port mode register 5 pm5 ff26h port mode register 6 pm6 ff28h port mode register 8 pm8 ff29h port mode register 9 pm9 ff30h pull-up resistor option register pu0 00h ff40h clock output selection register cks ff41h watch timer mode control register wtm ff42h watchdog timer clock select register wdcs ff48h external interrupt rising edge enable register egp ff49h external interrupt falling edge enable register egn ff4ah lcd timer control register lcdtm w ff61h compare register (sin side) mcmp10 r/w ff62h compare register (cos side) mcmp11 ff63h compare register (sin side) mcmp20 ff64h compare register (cos side) mcmp21 ff65h compare register (sin side) mcmp30 ff66h compare register (cos side) mcmp31 ff67h compare register (sin side) mcmp40 ff68h compare register (cos side) mcmp41 ff69h timer mode control register mcntc ff6ah port mode control register pmc ff6bh compare control register 1 mcmpc1 ff6ch compare control register 2 mcmpc2 ff6dh compare control register 3 mcmpc3 ff6eh compare control register 4 mcmpc4 ff70h prescaler mode register prm0 ff71h capture pulse control register crc0 ff72h 16-bit timer mode control register tmc0 ff73h timer clock select register 1 tcl1 ff74h timer clock select register 2 tcl2 ff75h timer clock select register 3 tcl3 table 3-5. special function register list (2/3)
54 chapter 3 cpu architecture address special-function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff76h 8-bit timer mode control register 1 tmc1 r/w 04h ff77h 8-bit timer mode control register 2 tmc2 ff78h 8-bit timer mode control register 3 tmc3 ff80h a/d converter mode register adm1 00h ff81h analog input channel specification register ads1 ff82h power-fail compare mode register pfm ff83h power-fail compare threshold value register pft ff84h serial operation mode register csim ff85h asynchronous serial interface mode register asim ff86h asynchronous serial interface status register asis r ff87h baud rate generator control register brgc r/w ff89h d/a converter mode register dam1 w ff90h eeprom write control register eewc r/w ff94h sound generator control register sgcr ff95h sound generator buzzer control register sgbr ff96h sound generator amplitude register sgam ffa0h oscillator mode register note 1 oscm ffb0h lcd display mode register lcdm ffb2h lcd display control register lcdc ffe0h interrupt request flag register 0l if0 if0l ffe1h interrupt request flag register 0h if0h ffe2h interrupt request flag register 1l if1l ffe4h interrupt mask flag register 0l mk0 mk0l ffh ffe5h interrupt mask flag register 0h mk0h ffe6h interrupt mask flag register 1l mk1l ffe8h priority specify flag register 0l pr0 pr0l ffe9h priority specify flag register 0h pr0h ffeah priority specify flag register 1l pr1l fff0h memory size switching register ims cfh note 2 fff9h watchdog timer mode register wdtm 00h fffah oscillation stabilization time select register osts 04h fffbh processor clock control register pcc notes 1. m pd780973(a) only 2. the initial value of this register is cfh. set the following value to this register of each model. m pd780973(a): 06h m pd78f0974 (to set the same memory map as m pd780973(a)): 06h table 3-5. special function register list (3/3)
55 chapter 3 cpu architecture 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of instructions, refer to 78k/0 series users manual instructions (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed twos complement data (C128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists in relative branching from the start address of the following instruction to the C128 to +127 range. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [operation] 15 0 pc + 15 0 876 s 15 0 pc a jdisp8 when s = 0, all bits of a are 0. when s = 1, all bits of a are 1. pc indicates the start address of the instruction after the br instruction. ...
56 chapter 3 cpu architecture 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branched to the 0800h to 0fffh area. [operation] in the case of call !addr16 and br !addr16 instructions in the case of callf !addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10C8 11 10 00001 643 callf fa 7C0
57 chapter 3 cpu architecture 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. this instruction references the address stored in the memory table from 40h to 7fh, and allows branching to the entire memory space. [operation] 3.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [operation] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4C0 operation code 70 rp 07 ax 15 0 pc 87
58 chapter 3 cpu architecture 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register which functions as an accumulator (a and ax) in the general register is automatically (implicitly) addressed. of the m pd780973 subseries instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu register a for multiplicand and register ax for product storage divuw register ax for dividend and quotient storage adjba/adjbs register a for storage of numeric values subject to decimal adjustment ror4/rol4 register a for storage of digit data subject to digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
59 chapter 3 cpu architecture 3.4.2 register addressing [function] the general register to be specified is accessed as an operand with the register specify code (rn and rpn) in an operation code and with the register bank select flags (rbs0 and rbs1). register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) as well as absolute names (r0 to r7 and rp0 to rp3). [description example] mov a, c; when selecting c register as r operation code 01100010 register specify code incw de; when selecting de register pair as rp operation code 10000100 register specify code
60 chapter 3 cpu architecture 3.4.3 direct addressing [function] the memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh [operation] memory 0 7 addr16 (lower) addr16 (upper) op code
61 chapter 3 cpu architecture 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. an internal high-speed ram and a special- function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. if the sfr area (ff00h to ff1fh) where short direct addressing is applied, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to [operation] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h operation code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) [operation] when 8-bit immediate data is 20h to ffh, a = 0 when 8-bit immediate data is 00h to 1fh, a = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset a
62 chapter 3 cpu architecture 3.4.5 special-function register (sfr) addressing [function] the memory-mapped special-function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special-function register name sfrp 16-bit manipulatable special-function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op code 00100000 20h (sfr-offset) [operation] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
63 chapter 3 cpu architecture 3.4.6 register indirect addressing [function] this addressing is to address a memory area to be manipulated by using as an operand address the contents of a register pair specified by the register bank select flags (rbs0 and rbs1) and the register pair specification code in the operation code. this addressing can be carried out for all the memory spaces. [operand format] identifier description [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [operation] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de
64 chapter 3 cpu architecture 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flags (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flags (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] operation code 10101011
65 chapter 3 cpu architecture 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. [description example] in the case of push de operation code 10110101
66 [memo]
67 chapter 4 eeprom 4.1 eeprom functions the m pd780973 subseries products contain on-chip 256 8-bit eeprom (electrically erasable prom) in addition to internal high-speed ram, as data memory. eeprom differs from ordinary ram in that its contents are saved even after power is cut off. moreover, unlike eprom, its contents can be erased electrically without using uv light. for this reason, it is suitable for applications where the setting values of the odometer and trip meter on the dash board are saved, etc. eeprom can be manipulated with 8-bit memory manipulation instructions. the eeprom contained on-chip in the m pd780973 subseries has the following features. (1) written contents are saved even when the power is cut off. (2) can be manipulated with 8-bit memory manipulation instructions in the same way as ordinary ram. (3) erasure and writing is performed in the time set with ewcs0 and ewcs1 (eeprom write control register (eewc) bits 4 and 5) (see figure 4-2). therefore, the write time control software load is reduced. moreover, during writing, instructions other than instructions related to eeprom writing and reading can also be executed. ? rewrite frequency for all chips : 1,000,000 times ? rewrite frequency per 1 byte : 100,000 times caution the values shown above are target values. these values are subject to change without notice, so please contact your nec sales representative for the latest value before designing. (4) when write is completed, interrupt request signal (intwe) is issued. (5) the write enabled/disabled status can be checked with ewst (eeprom write control register (eewc) bit 1).
68 chapter 4 eeprom 4.2 eeprom configuration eeprom is composed of eeprom itself and a control area. the control area consists of the eeprom write control register (eewc) that controls eeprom writing, and an area that generates an interrupt request signal (intwe) upon detecting write termination. figure 4-1. eeprom block diagram intwe ewcs1 ewcs0 ewcc ewe ewst eeprom (256 8 bits) prescaler read/write controller eeprom timer data latch f x internal bus eeprom write control register (eewc) address latch write termination
69 chapter 4 eeprom 4.3 eeprom control register eeprom is controlled with the eeprom write control register (eewc). eewc is set with either a 1-bit or 8-bit memory manipulation instruction. reset input sets eewc to 00h. figure 4-2. eeprom write control register (eewc) format address: ff90h after reset : 00h r/w symbol 76543210 eewc 0 0 ewcs1 ewcs0 0 ewcc ewst ewe ewcs1 ewcs0 eeprom write time 00(2 14 + 2 10 )/f x note 1 01(2 15 + 2 11 )/f x note 2 other than above setting prohibited ewcc eeprom operation control 0 operating mode 1 eeprom stop ewst eeprom write status 0 not currently writing to eeprom (eeprom write/read is enabled. however, when ewe = 0, write is disabled) 1 currently writing to eeprom (eeprom write/read is disabled) ewe eeprom write operation control 0 eeprom write disabled 1 eeprom write enabled notes 1. set the main system clock frequency (f x ) in the range of 4 to 5.120 mhz. 2. set the main system clock frequency (f x ) in the range of 5.364 to 8.38 mhz. cautions 1. if the main system clock frequency is set in the range of 5.120 < f x < 5.364 mhz, the eeprom cannot be used. 2. when ewe is cleared (to 0) during eeprom writing, writing is immediately interrupted. data that was being written becomes undefined. be sure to clear ewe before stopping the main system clock during the write period. 3. after ewcc is cleared (to 0), set a wait time of 20 m s or more by software to read eeprom contents. 4. be sure to check that ewst is 0 before performing eeprom access. 5. bits 3, 6, and 7 must be set to 0.
70 chapter 4 eeprom 4.4 eeprom reading reading of eeprom data is performed with the following procedure. <1> check that ewst (eeprom write control register (eewc) bit 1) is 0 (eeprom writing is not in progress). <2> execute read instruction. cautions 1. before reading, be sure to check that ewst is 0. if an eeprom read instruction is executed during eeprom write, read values are undefined. 2. if reading eeprom contents immediately after changing ewcc (eeprom write control register (eewc) bit 2) from 1 to 0, set a wait time of at least 20 m s by software. if no wait time is set, the correct values cannot be read. example: insertion of nop instructions to set wait time of 20 m s or more. clr1 ewcc nop insert nop instructions to secure a wait time of 20 m s or more. nop mov a,!0f800h y t
71 chapter 4 eeprom 4.5 eeprom writing data writing to eeprom is performed with the following procedure. <1> check that ewst (eeprom write control register (eewc) bit 1) is 0 (eeprom writing is not in progress). <2> set the write time with ewcs0 and ewcs1 (eewc bits 4 and 5). <3> set ewe (eewc bit 0) to 1 (eeprom writing enabled). <4> execute write instruction. if performing several write operations in succession, perform the next write operation after the current write operation has been completed. the following methods can be used for write termination and time control. (1) method using write termination interrupt request (intwe) after writing 1 data, wait for generation of write termination interrupt request while processing other than write is performed. when write termination interrupt request is generated, start next write operation. (2) method using write status flag (ewst) poll ewst (eeprom write control register (eewc) bit 1), and wait for ewst to become 0. when ewst becomes 0, start the next write operation. 4.6 eeprom control-related interrupt eeprom write termination interrupt request (intwe) is generated from eeprom. intwe is an interrupt request generated upon termination of eeprom writing. this interrupt request is generated when the time set with ewcs0 and ewcs1 (eeprom write control register (eewc) bits 4 and 5) has elapsed. when this interrupt request is generated, data writing to eeprom is terminated, indicating that writing of the next data is enabled.
72 chapter 4 eeprom 4.7 cautions regarding eeprom writing the following shows cautions of eeprom write. before performing eeprom write, be sure to read the following cautions. (1) before writing, be sure to check that ewst (eeprom write control register (eewc) bit 1) is 0. if executing another write instructions during eeprom writing, the instruction executed last will be ignored. (2) for write time, see figure 4-2. (3) if performing several write operations in succession, be sure to wait until the current write operation is completed before starting the next one. (4) even if the mode changes to halt mode during eeprom writing, writing is continued. (5) if the mode changes to stop mode during eeprom writing, the data being written becomes undefined. if this stop mode is cancelled by interrupt request, a write termination interrupt request (intwe) is generated after the stop mode has been cancelled. if you want to set the stop mode after normally terminating write processing, check that write processing has ended using any of the available methods (refer to 4.5 eeprom writing ), then set the stop mode. (6) if you want to read the eeprom contents immediately after changing ewcc (eeprom write control register (eewc) bit 2) from 1 to 0, set a wait time of 20 m s or more by software. if no wait time is set, the data read will not be correct.
73 chapter 5 port functions 5.1 port functions the m pd780973 subseries are provided with five input port pins, sixteen output port pins, and thirty-five input/output port pins. figure 5-1 shows the port configuration. every port can be manipulated in 1-bit or 8-bit units controlled in various ways. moreover, the port pins can also serve as i/o pins of the internal hardware. figure 5-1. port types p00 ? ? ? ? ? ? ? port 0 p10 ? ? ? ? ? port 1 p14 p20 port 2 p27 p30 ? ? ? port 4 ? ? ? port 5 ? port 6 ? ? ? ? ? ? ? port 9 p40 p44 p50 p54 p60 p61 ? ? ? ? ? ? ? port 8 p81 p87 p90 p97 ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 3 p37 p07
74 chapter 5 port functions table 5-1. port functions pin name input/output function alternate function p00 to p02 input/output intp0 to intp2 p03 to p07 p10 to p14 input port 1 ani0 to ani4 5-bit input only port. p20 to p23 output port 2 sm11 to sm14 p24 to p27 8-bit output only port. sm21 to sm24 p30 to p33 output port 3 sm31 to sm34 p34 to p37 8-bit output only port. sm41 to sm44 p40 to p42 input/output ti00 to ti02 p43, p44 tio2, tio3 p50 input/output port 5 sck p51 5-bit input/output port. so p52 input/output mode can be specified bit-wise. si p53 rxd p54 txd p60 input/output pcl/sgoa p61 sgo/sgof p81 input/output s19/tpo p82 to p87 s18 to s13 p90 to p97 input/output port 9 s12 to s5 8-bit input/output port. input/output mode can be specified bit-wise. can be set in input/output port or segment output mode in 2-bit units by using lcd display control register (lcdc). port 0 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 4 5-bit input/output port. input/output mode can be specified bit-wise. port 6 2-bit input/output port. input/output mode can be specified bit-wise. port 8 7-bit input/output port. input/output mode can be specified bit-wise. can be set in input/output port or segment output mode in 2-bit units by using lcd display control register (lcdc).
75 chapter 5 port functions 5.2 port configuration a port consists of the following hardware: table 5-2. port configuration item configuration control register port mode register (pmm: m = 0, 2 to 6, 8, 9) pull-up resistor option register (pu0) port total: 56 lines (5 inputs, 16 outputs, 35 inputs/outputs) pull-up resistor total: 8 (software specifiable: 8) 5.2.1 port 0 port 0 is an 8-bit input/output port with output latch. p00 to p07 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (pm0). when p00 to p07 pins are used as input ports, an on-chip pull-up resistor can be used to them in 1-bit units with a pull-up resistor option register (pu0). alternate functions include external interrupt request input. reset input sets port 0 to input mode. figure 5-2 shows a block diagram of port 0. caution because port 0 also serves for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1.
76 chapter 5 port functions figure 5-2. p00 to p07 block diagram rd p00/intp0 p02/intp2 p03 to p07 p-ch wr puo wr port wr pm pu00 to pu07 output latch (p00 to p07) pm00 to pm07 selector v dd internal bus pu : pull-up resistor option register pm : port mode register rd : port 0 read signal wr : port 0 write signal 5.2.2 port 1 port 1 is a 5-bit input only port. alternate functions include an a/d converter analog input. figure 5-3 shows a block diagram of port 1. figure 5-3. p10 to p14 block diagram rd p10/ani0 p14/ani4 internal bus rd : port 1 read signal
77 chapter 5 port functions 5.2.3 port 2 port 2 is an 8-bit output only port with output latch. p20 to p27 pins go into a high-impedance state when the enn of port mode control register (pmc) is set to 0 and the port mode register 2 (pm2) is set to 1. alternate functions include meter control pwm output. reset input sets port 2 to high-impedance state. figure 5-4 shows a block diagram of port 2. figure 5-4. p20 to p27 block diagram pm : port mode register rd : port 2 read signal wr : port 2 write signal caution when pm2 is set to 0, read operation is enabled. when pm2 is set to 1, read operation is disabled. remark n = 1, 2 p20/sm11 to p23/sm14 p24/sm21 to p27/sm24 wr port wr pm output latch (p20 to p27) selector decoder pm20 to pm27 2 alternate functions internal bus rd dirn1 dirn0 modn enn
78 chapter 5 port functions 5.2.4 port 3 port 3 is an 8-bit output only port with output latch. p30 to p37 pins go into a high-impedance state when the enn of port mode control register (pmc) is set to 0 and the port mode register 3 (pm3) is set to 1. alternate functions include meter control pwm output. reset input sets port 3 to high-impedance state. figure 5-5 shows a block diagram of port 3. figure 5-5. p30 to p37 block diagram pm : port mode register rd : port 3 read signal wr : port 3 write signal caution when pm3 is set to 0, read operation is enabled. when pm3 is set to 1, read operation is disabled. remark n = 3, 4 p30/sm31 to p33/sm34 p34/sm41 to p37/sm44 wr port wr pm output latch (p30 to p37) pm30 to pm37 alternate functions internal bus rd selector decoder 2 dirn1 dirn0 modn enn
79 chapter 5 port functions 5.2.5 port 4 port 4 is a 5-bit input/output port with output latch. p40 to p44 pins can specify the input mode/output mode in 1-bit units with the port mode register 4 (pm4). alternate functions also include timer input/output. reset input sets port 4 to input mode. figure 5-6 shows a block diagram of port 4. figure 5-6. p40 to p44 block diagram pm : port mode register rd : port 4 read signal wr : port 4 write signal rd p40/ti00 to p42/ti02 p43/tio2 p44/tio3 wr port wr pm output latch (p40 to p44) pm40 to pm44 alternate functions selector internal bus
80 chapter 5 port functions 5.2.6 port 5 port 5 is a 5-bit input/output port with output latch. p50 to p54 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (pm5). alternate functions include serial interface data input/output and clock input/output. reset input sets port 5 to input mode. figure 5-7 shows a block diagram of port 5. figure 5-7. p50 to p54 block diagram pm : port mode register rd : port 5 read signal wr : port 5 write signal rd p50/sck p51/so p52/si p53/rxd p54/txd wr port wr pm output latch (p50 to p54) pm50 to pm54 alternate functions selector internal bus
81 chapter 5 port functions 5.2.7 port 6 port 6 is a 2-bit input/output port with output latch. p60 and p61 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (pm6). alternate functions include clock output and sound generator output. reset input sets port 6 to input mode. figure 5-8 shows a block diagram of port 6. figure 5-8. p60 and p61 block diagram pm : port mode register rd : port 6 read signal wr : port 6 write signal rd p60/pcl/sgoa p61/sgo/sgof wr port wr pm output latch (p60, p61) pm60, pm61 alternate functions selector internal bus
82 chapter 5 port functions 5.2.8 port 8 port 8 is a 7-bit input/output port with output latch. p81 to p87 pins can specify the input mode/output mode in 1-bit units with the port mode register 8 (pm8). alternate functions also include segment signal output of the lcd controller/driver and prescaler signal output. segment output and input/output port can be switched by setting the lcd display control register (lcdc). reset input sets port 8 to input mode. figures 5-9 and 5-10 show block diagrams of port 8. figure 5-9. p81 block diagram figure 5-10. p82 to p87 block diagram pm : port mode register rd : port 8 read signal wr : port 8 write signal rd p81/s19/tpo wr port wr pm pm81 selector output latch (p81) internal bus segment output function alternate functions rd p82/s18 to p87/s13 wr port wr pm pm82 to pm87 selector output latch (p82 to p87) internal bus segment output function
83 chapter 5 port functions 5.2.9 port 9 port 9 is an 8-bit input/output port with output latch. p90 to p97 pins can specify the input mode/output mode in 1-bit units with the port mode register 9 (pm9). alternate functions also include segment signal output of the lcd controller/driver. segment output and input/output port can be switched by setting the lcd display control register (lcdc). reset input sets port 9 to input mode. figure 5-11 shows a block diagram of port 9. figure 5-11. p90 to p97 block diagram pm : port mode register rd : port 9 read signal wr : port 9 write signal rd p90/s12 to p97/s5 wr port wr pm pm90 to pm97 selector output latch (p90 to p97) internal bus segment output function
84 chapter 5 port functions 5.3 port function control registers the following two types of registers control the ports. ? port mode registers (pm0, pm2 to pm6, pm8, pm9) ? pull-up resistor option register (pu0) (1) port mode registers (pm0, pm2 to pm6, pm8, pm9) these registers are used to set port input/output in 1-bit units. pm0, pm2 to pm6, pm8, and pm9 are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets registers to ffh. cautions 1. pins p10 and p14 are input-only pins, and pins p20 to p27 and p30 to p37 are output- only pins. 2. port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 3. ports 2 and 3 that can be also used as meter driving pwm signal output pins go into a high-impedance state when 1 is set to pm2 and pm3 , respectively.
85 chapter 5 port functions table 5-3. port mode register and output latch settings when using alternate functions notes 1. if these ports are read out when these pins are used in the alternate function mode, undefined values are read. 2. the p20 to p27 and p30 to p37 pins have an alternate function as meter driving pwm signal output. when 0 is set to enn (n = 1 to 4) of port mode control register (pmc) and 1 is set to pm , these pins go into the high-impedance state. refer to the port mode register format. 3. when the p81 to p87 and p90 to p97 pins are used for alternate functions, set the function with the lcd display control register (lcdc). caution when port 5 is used for serial interface, the i/o latch or output latch must be set according to their function. for the setting methods, see figure 14-2 asynchronous serial interface mode register (asim) format and figure 15-2 serial operation mode register (csim) format. remark : dont care pm : port mode register p : port output latch p00 intp0 input 1 p01 intp1 input 1 p02 intp2 input 1 p10 to p14 note 1 ani0 to ani4 input 1 p20 to p27 sm11 to sm24 output 0 note 2 p30 to p37 sm31 to sm44 output 0 note 2 p40 to p42 ti00 to ti02 input 1 p43, p44 tio2, tio3 output 0 0 p60 sgoa/pcl output 0 0 p61 sgo/sgof output 0 0 p81, p82 to p87 s19/tpo, s18 to s13 output note 3 p90 to p97 s12 to s5 output note 3 alternate functions name p pm input/output pin name
86 chapter 5 port functions figure 5-12. port mode register (pm0, pm4 to pm6, pm8, pm9) format address: ff20h after reset : ffh r/w symbol 76543210 pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 address: ff24h after reset : ffh r/w symbol 76543210 pm4 1 1 1 pm44 pm43 pm42 pm41 pm40 address: ff25h after reset : ffh r/w symbol 76543210 pm5 1 1 1 pm54 pm53 pm52 pm51 pm50 address: ff26h after reset : ffh r/w symbol 76543210 pm6 111111 pm61 pm60 address: ff28h after reset : ffh r/w symbol 76543210 pm8 pm87 pm86 pm85 pm84 pm83 pm82 pm81 1 address: ff29h after reset : ffh r/w symbol 76543210 pm9 pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pmmn pmn pin input/output mode select (m = 0, 4 to 6, 8, 9 ; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 5-13. port mode register (pm2, pm3) format address: ff22h after reset : ffh r/w symbol 76543210 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 address: ff23h after reset : ffh r/w symbol 76543210 pm3 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pmmn pmn pin input/output mode select (m = 2, 3 ; n = 0 to 7) 0 output mode (output buffer on) 1 high-impedance state (output buffer off) note note when 0 is set to enn of port mode control register (pmc)
87 chapter 5 port functions (2) pull-up resistor option register (pu0) this register is used to set whether to use an internal pull-up resistor at port 0 or not. a pull-up resistor is internally used at bits which are set to the input mode at a port where pull-up resistor use has been specified with pu0. no pull-up resistors can be used to the bits set to the output mode irrespective of pu0 setting. pu0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-14. pull-up resistor option register (pu0) format address: ff30h after reset : 00h r/w symbol 76543210 pu0 pu07 pu06 pu05 pu04 pu03 pu02 pu01 pu00 pu0m p0m pin internal pull-up resistor select (m = 0 to 7) 0 on-chip pull-up resistor not used 1 on-chip pull-up resistor used
88 chapter 5 port functions 5.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 writing to input/output port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 5.4.2 reading from input/output port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 5.4.3 operations on input/output port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
89 chapter 6 clock generator 6.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. ? main system clock oscillator this circuit oscillates at frequencies of 4.19 to 8.38 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). 6.2 clock generator configuration the clock generator consists of the following hardware. table 6-1. clock generator configuration item configuration control register processor clock control register (pcc) oscillator mode register (oscm) note oscillator main system clock oscillator note m pd780973(a) only figure 6-1. clock generator block diagram x1 x2 main system clock oscillator halfosc f x prescaler f x 2 f x 2 2 f x 2 3 f x 2 4 prescaler clock to peripheral hardware cpu clock (f cpu ) standby control circuit selector stop pcc2 pcc1 3 pcc0 processor clock control register oscillator mode register internal bus
90 chapter 6 clock generator 6.3 clock generator control register the following two types of registers are used to control the clock generator. ? processor clock control register (pcc) ? oscillator mode register (oscm) (1) processor clock control register (pcc) the pcc sets the division ratio of the cpu clock. the pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the pcc to 04h. figure 6-2. processor clock control register (pcc) format address: fffbh after reset: 04h r/w symbol 76543210 pcc 00000 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 cpu clock (f cpu ) select 000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 other than above setting prohibited caution bits 3 to 7 must be set to 0. remark f x : main system clock oscillation frequency the fastest instructions of the m pd780973 subseries are executed in two cpu clocks. therefore, the relation between the cpu clock (f cpu ) and the minimum instruction execution time is as shown in table 6-2. table 6-2. relation between cpu clock and minimum instruction execution time cpu clock (f cpu ) minimum instruction execution time: 2/f cpu f x = 8 mhz f x = 8.38 mhz f x 0.25 m s 0.24 m s f x /2 0.5 m s 0.48 m s f x /2 2 1.0 m s 0.95 m s f x /2 3 2.0 m s 1.91 m s f x /2 4 4.0 m s 3.81 m s remark f x : main system clock oscillation frequency
91 chapter 6 clock generator (2) oscillator mode register (oscm) the m pd780973(a) can be set to the reduced current consumption mode by setting oscm (only when operated at f x = 4 to 4.19 mhz). oscm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets oscm to 00h. figure 6-3. oscillator mode register (oscm) format address: ffa0h after reset: 00h r/w symbol 76543210 oscm halfosc 0000000 halfosc oscillator mode selection 0 normal operation mode 1 reduced current consumption mode (only when operated at f x = 4 to 4.19 mhz) cautions 1. this function is available only when the device is operated at f x = 4 to 4.19 mhz. in other cases, be sure not to set 1 to bit 7. 2. when using in normal operation mode, setting oscm is not necessary. 3. only the first setting of oscm is effective.
92 chapter 6 clock generator 6.4 system clock oscillator 6.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.38 mhz) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and an inverted clock signal to the x2 pin. figure 6-4 shows an external circuit of the main system clock oscillator. figure 6-4. external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock crystal resonator or ceramic resonator x2 x1 pd74hcu04 external clock x2 x1 ic m caution do not execute the stop instruction while an external clock is input. this is because if the stop instruction is executed, the main system clock operation is stopped, and the x2 pin is connected to v dd , via a pull-up resistor.
93 chapter 6 clock generator caution when using a main system clock oscillator, carry out wiring in the broken line area in figure 6-4 as follows to avoid influence of wiring capacity. keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. always keep the ground of the capacitor of the oscillator at the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. figure 6-5 shows examples of resonator having bad connection. figure 6-5. incorrect examples of resonator connection (1/2) (a) too long wiring (b) crossed signal line x1 ic x2 x2 ic x1 portn (n = 0 to 6, 8 and 9)
94 chapter 6 clock generator figure 6-5. incorrect examples of resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) ic x2 x1 ic x2 x1 ab c pmn v dd high current high current (e) signals are fetched ic x2 x1 6.4.2 divider circuit the divider circuit divides the output of the main system clock oscillation circuit (f x ) to generate various clocks.
95 chapter 6 clock generator 6.5 operation of clock generator the clock generator generates the following clocks and controls the operation modes of the cpu, such as the standby mode: ? main system clock f x ? cpu clock f cpu ? clock to peripheral hardware the operation of the clock generator is determined by the processor clock control register (pcc) and oscillator mode register (oscm) as follows: (a) the slowest mode (3.81 m s: at 8.38-mhz operation) of the main system clock is selected when the reset signal is generated (pcc = 04h). while a low level is input to the reset pin, oscillation of the main system clock is stopped. (b) five types of cpu clocks (0.24 m s, 0.48 m s, 0.95 m s, 1.91 m s, and 3.81 m s: at 8.38-mhz operation) can be selected by the pcc setting. (c) two standby modes, stop and halt, can be used. (d) the clock to the peripheral hardware is supplied by dividing the main system clock. the other peripheral hardware is stopped when the main system clock is stopped (except, however, the external clock input operation). (e) the m pd780973(a) can be set to the reduced current consumption mode by setting oscm (only when operated at f x = 4 to 4.19 mhz). setting 1 to bit 7 (halfosc) of oscm will reduce the power consumption. cautions 1. this function is available only when the device is operated at f x = 4 to 4.19 mhz. in other cases, be sure not to set 1 to bit 7. 2. when using in normal operation mode, setting oscm is not necessary. 3. only the first setting of oscm is effective.
96 chapter 6 clock generator 6.6 changing setting of cpu clock 6.6.1 time required for switching cpu clock the cpu clock can be selected by using bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc). actually, the specified clock is not selected immediately after the setting of pcc has been changed, and the old clock is used for the duration of several instructions after that (refer to table 6-3 ). table 6-3. maximum time required for switching cpu clock set value after switching pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 000001010011100 0 0 0 16 instructions 16 instructions 16 instructions 16 instructions 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction remark one instruction is the minimum instruction execution time of the cpu clock before switching. set value before switching
97 chapter 6 clock generator 6.6.2 switching cpu clock the following figure illustrates how the cpu clock switches. figure 6-6. switching cpu clock v dd reset cpu clock slowest operation fastest operation wait (15.6 ms: at 8.38-mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on power application. the effect of resetting is released when the reset pin is later made high, and the main system clock starts oscillating. at this time, the time during which oscillation stabilizes (2 17 /f x ) is automatically secured. after that, the cpu starts instruction execution at the slowest speed of the main system clock (3.81 m s: at 8.38-mhz operation). <2> after the time during which the v dd voltage rises to the level at which the cpu can operate at the highest speed has elapsed, pcc is rewritten so that the highest speed can be selected.
98 [memo]
99 chapter 7 16-bit timer 0 tm0 7.1 outline of internal timer of m pd780973 subseries this chapter explains the 16-bit timer 0. before that, the internal timers of the m pd780973 subseries, and the related functions are briefly explained below. (1) 16-bit timer 0 tm0 the tm0 can be used for pulse widths measurement, divided output of input pulse. (2) 8-bit timer 1 tm1 the tm1 can be used for an interval timer (see chapter 8 8-bit timer 1 tm1 ). (3) 8-bit timer/event counters 2, 3 tm2, tm3 tm2 and tm3 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency, pwm output (see chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 ). (4) watch timer this timer can set a flag every 0.5 sec. and simultaneously generates interrupt request at the preset time intervals (see chapter 10 watch timer ). (5) watchdog timer this timer can perform the watchdog timer function or generate non-maskable interrupt request, maskable interrupt request and reset at the preset time intervals (see chapter 11 watchdog timer ). (6) clock output control circuit clock output supplies other devices with the divided main system clock (see chapter 12 clock output control circuit ).
100 chapter 7 16-bit timer 0 tm0 table 7-1. timer/event counter operations 16-bit timer tm0 8-bit timer tm1 8-bit timer/event watch timer watchdog timer counter tm2, tm3 operating interval timer C 1 channel 2 channels 1 channel note 1 1 channel note 2 mode external event counter C C CC function timer output C C CC pwm output C C CC pulse width measurement CCCC square-wave output C C CC divided output CCCC interrupt request notes 1. watch timer can perform both watch timer and interval timer functions at the same time. 2. watchdog timer can perform either the watchdog timer function or the interval timer function, as selected. 7.2 16-bit timer 0 functions the 16-bit timer 0 (tm0) has the following functions. ? pulse width measurement ? divided output of input pulse figure 7-1 shows 16-bit timer 0 block diagram.
101 chapter 7 16-bit timer 0 tm0 figure 7-1. timer 0 (tm0) block diagram (1) pulse width measurement tm0 can measure the pulse width of an externally input signal. (2) divided output of input pulse the frequency of an input signal can be divided and the divided signal can be output. internal bus internal bus 16-bit timer register (tm0) 16-bit capture register (cr02) edge detection circuit edge detection circuit edge detection circuit es01, es00 tpoe es11, es10 es21, es20 16-bit capture register (cr01) 16-bit capture register (cr00) intovf inttm02 inttm01 inttm00 es21 es20 es11 f x /8 f x /16 f x /32 f x /64 es10 es01 crc01 tmc02 tpoe crc00 es00 prm01 prm00 prescaler mode register (prm0) capture pulse control register (crc0) 16-bit timer mode control register (tmc0) selector ti02/p42 ti01/p41 ti00/p40 tpo/p81/s19 prescaler 1, 1/2, 1/4, 1/8 noise rejection circuit noise rejection circuit noise rejection circuit
102 chapter 7 16-bit timer 0 tm0 7.3 16-bit timer 0 configuration timer 0 consists of the following hardware. table 7-2. timer 0 configuration item configuration timer register 16 bits 1 (tm0) register capture register: 16 bits 3 (cr00 to cr02) control register 16-bit timer mode control register (tmc0) capture pulse control register (crc0) prescaler mode register (prm0) (1) 16-bit timer register (tm0) tm0 is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of an input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases: <1> at reset input <2> if tmc02 is cleared (2) capture register 00 (cr00) the valid edge of the ti00 pin can be selected as the capture trigger. setting of the ti00 valid edge is performed by setting of the prescaler mode register (prm0). when the valid edge of the ti00 is detected, an interrupt request (inttm00) is generated. cr00 is read by a 16-bit memory manipulation instruction. after reset input, the value of cr00 is undefined. (3) capture register 01 (cr01) the valid edge of the ti01 pin can be selected as the capture trigger. setting of the ti01 valid edge is performed by setting of the prescaler mode register (prm0). when the valid edge of the ti01 is detected, an interrupt request (inttm01) is generated. cr01 is read by a 16-bit memory manipulation instruction. after reset input, the value of cr01 is undefined. (4) capture register 02 (cr02) the valid edge of the ti02 pin can be selected as the capture trigger. setting of the ti02 valid edge is performed by setting of the prescaler mode register (prm0). when the valid edge of the ti02 is detected, an interrupt request (inttm02) is generated. cr02 is read by a 16-bit memory manipulation instruction. after reset input, the value of cr02 is undefined.
103 chapter 7 16-bit timer 0 tm0 7.4 16-bit timer 0 control registers the following three types of registers are used to control timer 0. ? 16-bit timer mode control register (tmc0) ? capture pulse control register (crc0) ? prescaler mode register (prm0) (1) 16-bit timer mode control register (tmc0) this register sets the 16-bit timer operating mode and controls the prescaler output signals. tmc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc0 value to 00h. figure 7-2. 16-bit timer mode control register (tmc0) format address: ff72h after reset: 00h r/w symbol 76543210 tmc0 00000 tmc02 0 tpoe tmc02 timer 0 operating mode selection 0 operation stop (tm0 cleared to 0) 1 operation enabled tpoe timer 0 prescaler output control 0 prescaler signal output disabled 1 prescaler signal output enabled cautions 1. before changing the operation mode, stop the timer operation (by setting 0 to tmc02). 2. bit 1 and bits 3 to 7 must be set to 0.
104 chapter 7 16-bit timer 0 tm0 (2) capture pulse control register (crc0) this register specifies the division ratio of the capture pulse input to the 16-bit capture register (cr02) from an external source. crc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets crc0 value to 04h. figure 7-3. capture pulse control register (crc0) format address: ff71h after reset: 00h r/w symbol 76543210 crc0 000000 crc01 crc00 crc01 crc00 capture pulse selection 0 0 does not divide capture pulse 0 1 divides capture pulse by 2 1 0 divides capture pulse by 4 1 1 divides capture pulse by 8 cautions 1. timer operation must be stopped before setting crc0. 2. bits 2 to 7 must be set to 0.
105 chapter 7 16-bit timer 0 tm0 (3) prescaler mode register (prm0) this register is used to set 16-bit timer (tm0) count clock and valid edge of ti0n (n = 0 to 2) input. prm0 is set with an 8-bit memory manipulation instruction. reset input sets prm0 value to 00h. figure 7-4. prescaler mode register (prm0) format address: ff70h after reset: 00h r/w symbol 76543210 prm0 es21 es20 es11 es10 es01 es00 prm01 prm00 es21 es20 ti02 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es11 es10 ti01 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es01 es00 ti00 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm01 prm00 count clock selection 00f x /2 3 01f x /2 4 10f x /2 5 11f x /2 6 caution timer operation must be stopped before setting prm0.
106 chapter 7 16-bit timer 0 tm0 7.5 16-bit timer 0 operations 7.5.1 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00/p40 to ti02/p42 pins using the 16-bit timer register (tm0). tm0 is used in free-running mode. (1) pulse width measurement with free-running counter and one capture register (ti00) when the edge specified by prescaler mode register (prm0) is input to the ti00/p40 pin, the value of tm0 is taken into 16-bit capture register 00 (cr00) and an external interrupt request signal (inttm00) is set. any of three edge specifications can be selectedrising, falling, or both edgesby means of bits 2 and 3 (es00 and es01) of prm0. for valid edge detection, sampling is performed at the count clock selected by prm0, and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 7-5. configuration diagram for pulse width measurement by free-running counter f x /2 3 f x /2 4 f x /2 5 f x /2 6 ti00 16-bit timer register (tm0) intovf 16-bit capture register 00 (cr00) internal bus inttm00 selector figure 7-6. timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) t count clock tm0 count value value loaded to cr00 intovf 0000h 0001h d0 d1 ffffh 0000h d2 d3 d3 d2 d1 d0 (d1 C d0) t (10000h e d1 + d2) t (d3 e d2) t ti00 pin input inttm00
107 chapter 7 16-bit timer 0 tm0 (2) measurement of three pulse widths with free-running counter the 16-bit timer register (tm0) allows simultaneous measurement of the pulse widths of the three signals input to the ti00/p40 to ti02/p42 pins. when the edge specified by bits 2 and 3 (es00 and es01) of prescaler mode register (prm0) is input to the ti00/p40 pin, the value of tm0 is taken into 16-bit capture register 00 (cr00) and an external interrupt request signal (inttm00) is set. also, when the edge specified by bits 4 and 5 (es10 and es11) of prm0 is input to the ti01/p41 pin, the value of tm0 is taken into 16-bit capture register 01 (cr01) and an external interrupt request signal (inttm01) is set. when the edge specified by bits 6 and 7 (es20 and es21) of prm0 is input to the ti02/p42 pin, the value of tm0 is taken into 16-bit capture register 02 (cr02) and external interrupt request signal (inttm02) is set. any of three edge specifications can be selectedrising, falling, or both edgesas the valid edges for the ti00/ p40 to ti02/p42 pins by means of bits 2 and 3 (es00 and es01), bits 4 and 5 (es10 and es11), and bits 6 and 7 (es06 and es07) of prm0, respectively. for ti00/p40 pin valid edge detection, sampling is performed at the interval selected by means of the prescaler mode register (prm0), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. ? capture operation capture register operation in capture trigger input is shown. figure 7-7. cr0m capture operation with rising edge specified count clock tm0 ti0m rising edge detection cr0m inttm0m nC3 nC2 nC1 n n+1 n remark m = 0 to 2
108 chapter 7 16-bit timer 0 tm0 figure 7-8. timing of pulse width measurement operation by free-running counter (with both edges specified) count clock tm0 count value ti0m pin input value loaded to cr0m inttm0m ti0n pin input value loaded to cr0n inttm0n intovf (d1 e d0) t (10000h e d0 + d2) t (10000h e d1 + (d2 + 1) t (d3 e d2) t t 0000h 0001h d0 d1 ffffh 0000h d2 d3 d3 d1 d0 d1 d2 remark m = 0 to 2, n = 1, 2
109 chapter 7 16-bit timer 0 tm0 7.6 16-bit timer 0 cautions (1) timer start errors an error with a maximum of one clock may occur until counting is started after timer start. this is because the 16-bit timer register (tm0) is started asynchronously with the count pulse. figure 7-9. 16-bit timer register start timing tm0 count value 0000h 0001h 0002h 0004h count pulse timer start 0003h (2) capture register data retention timings if the valid edge of the ti0m/p4m pin is input during 16-bit capture register 0m (cr0m) read, cr0m performs capture operation, but the capture value is not guaranteed. however, the interrupt request flag (inttm0m) is set upon detection of the valid edge. figure 7-10. capture register data retention timing count pulse tm0 count value edge input interrupt request flag capture read signal cr0m interrupt value n n+1 n+2 m m+1 m+2 x n+1 capture operation remark m = 0 to 2 (3) valid edge setting set the valid edge of the ti0m/p4m pin after setting bit 2 (tmc02) of the 16-bit timer mode control register to 0, and then stopping timer operation. valid edge setting is carried out with bits 2 to 7 (esm0 and esm1) of the prescaler mode register (prm0). remark m = 0 to 2
110 chapter 7 16-bit timer 0 tm0 (4) occurrence of inttm0n inttm0n occurs even if no capture pulse exists, immediately after the timer operation has been started (tmc02 of tmc0 has been set to 1) with a high level applied to input pins ti00 to ti02 of 16-bit timer 0, and with the rising edge (with esn1 and esn0 of prm0 set to 0, 1), or both the rising and falling edges (with esn1 and esn0 of prm0 set to 1, 1) selected. however, inttm0n does not occur if a low level is applied to ti00 to ti02.
111 chapter 8 8-bit timer 1 tm1 8.1 8-bit timer 1 functions the 8-bit timer 1 operates as an 8-bit interval timer. figure 8-1 shows timer 1 block diagram. figure 8-1. timer 1 (tm1) block diagram internal bus internal bus 8-bit compare register 1 (cr1) 8-bit counter (tm1) clear coincidence inttm1 3 timer mode control register (tmc1) timer clock select register 1 (tcl1) tce1 tcl12 tcl11 tcl10 f x /2 3 f x /2 4 f x /2 5 f x /2 7 f x /2 9 f x /2 11 selector
112 chapter 8 8-bit timer 1 tm1 8.2 8-bit timer 1 configuration timer 1 consists of the following hardware. table 8-1. timer 1 configuration item configuration timer register 8-bit counter 1 (tm1) register 8-bit compare register 1 (cr1) control register timer clock select register 1 (tcl1) 8-bit timer mode control register 1 (tmc1) remark n = 0, 1 (1) 8-bit counter 1 (tm1) tm1 is an 8-bit read-only register which counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. when count value is read during operation, count clock input is temporary stopped, and then the count value is read. in the following situations, the count value is set to 00h. <1> reset input <2> clear tce1 <3> match between tm1 and cr1 (2) 8-bit compare register 1 (cr1) the value set in the cr1 is constantly compared with the 8-bit counter 1 (tm1) count value, and an interrupt request (inttm1) is generated if they match. it is possible to rewrite the value of cr1 within 00h to ffh during count operation.
113 chapter 8 8-bit timer 1 tm1 8.3 8-bit timer 1 control registers the following two types of registers are used to control timer 1. ? timer clock select register 1 (tcl1) ? 8-bit timer mode control register 1 (tmc1) (1) timer clock select register 1 (tcl1) this register sets count clocks of timer 1. tcl1 is set with an 8-bit memory manipulation instruction. reset input clears to 00h. figure 8-2. timer clock select register 1 (tcl1) format address: ff73h after reset: 00h r/w symbol 76543210 tcl1 00000 tcl12 tcl11 tcl10 tcl12 tcl11 tcl10 count clock selection 0 0 0 setting prohibited 0 0 1 setting prohibited 010f x /2 3 (1.04 mhz) 011f x /2 4 (523 khz) 100f x /2 5 (261 khz) 101f x /2 7 (65.4 khz) 110f x /2 9 (16.3 khz) 111f x /2 11 (4.09 khz) cautions 1. when rewriting tcl1 to other data, stop the timer operation beforehand. 2. set bits 3 to 7 to 0. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.38 mhz
114 chapter 8 8-bit timer 1 tm1 (2) 8-bit timer mode control register 1 (tmc1) tmc1 is a register that controls the counting operation of the 8-bit counter 1 (tm1). tmc1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets to 04h. figure 8-3 shows tmc1 format. figure 8-3. 8-bit timer mode control register 1 (tmc1) format address: ff76h after reset: 04h r/w symbol 76543210 tmc1 tce1 0000100 tce1 timer 1 count operation control 0 after clearing counter to 0, count operation disabled 1 count operation start caution be sure to set 0 to bit 0, bit 1, and bits 3 to 6, and set 1 to bit 2.
115 chapter 8 8-bit timer 1 tm1 8.4 8-bit timer 1 operations 8.4.1 8-bit interval timer operation the 8-bit timer 1 operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to 8-bit compare register 1 (cr1). when the count values of the 8-bit counter 1 (tm1) match the values set to cr1, counting continues with the tm1 values cleared to 0 and the interrupt request signal (inttm1) is generated. count clock of the tm1 can be selected with bits 0 to 2 (tcl10 to tcl12) of the timer clock select register 1 (tcl1). [setting] <1> set the registers. ? tcl1 : select count clock. ? cr1 : compare value <2> after tce1 = 1 is set, count operation starts. <3> if the values of tm1 and cr1 match, the inttm1 is generated and tm1 is cleared to 00h. <4> inttm1 generates repeatedly at the same interval. set tce1 to 0 to stop count operation. figure 8-4. interval timer operation timings (1/3) (a) basic operation t count clock tm1 count value cr1 tce1 inttm1 tm1 interval time note start count clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt received interrupt received interval time interval time interval time remark interval time = (n + 1) t: n = 00h to ffh
116 chapter 8 8-bit timer 1 tm1 figure 8-4. interval timer operation timings (2/3) (b) when cr1 = 00h t count clock tm1 cr1 tce1 inttm1 tm1 interval time interval time 00h 00h 00h 00h 00h (c) when cr1 = ffh t count clock tm1 cr1 tce1 inttm1 tm1 interval time 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt received interrupt received
117 chapter 8 8-bit timer 1 tm1 figure 8-4. interval timer operation timings (3/3) (d) operated by cr1 transition (m < n) count clock tm1 cr1 tce1 inttm1 tm1 interval time 00h n n m n ffh 00h m 00h m cr1 transition tm1 overflows since m < n (e) operated by cr1 transition (m > n) count clock tm1 cr1 tce1 inttm1 tm1 interval time n? n n 00h 01h n m? m 00h 01h m cr1 transition
118 chapter 8 8-bit timer 1 tm1 8.5 8-bit timer 1 cautions (1) timer start errors an error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. this is because 8-bit counter 1 (tm1) is started asynchronously with the count pulse. figure 8-5. timer 1 start timing count pulse tm1 count value 00h 01h 02h 03h 04h timer start (2) operation after compare register change during timer count operation if the values after the 8-bit compare register 1 (cr1) is changed are smaller than the value of 8-bit timer register 1 (tm1), tm1 continues counting, overflows and then restarts counting from 0. thus, if the value (m) after cr1 change is smaller than value (n) before the change, it is necessary to restart the timer after changing cr1. figure 8-6. timing after compare register change during timer count operation count pulse cr1 tm1 count value nm x? x ffh 00h 01h 02h remark n > x > m caution always set tce1 = 0 before setting the stop state. (3) tm1 reading during timer operation when tm1 is read during operation, choose a count clock which has a longer high/low level wave because 8- bit counter (tm1) is stopped temporary.
119 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 9.1 8-bit timer/event counters 2 and 3 functions the 8-bit timer/event counters 2 and 3 operate as an 8-bit timer/event counter. tm2 and tm3 can have the following functions. ? interval timer ? external event counter ? square wave output ? pwm output figure 9-1 shows timer 2 block diagram, and figure 9-2 shows timer 3 block diagram. figure 9-1. timer 2 (tm2) block diagram note bit 3 of port mode register (pm4) internal bus 8-bit compare register 2 (cr2) 8-bit counter 2 (tm2) tio2/p43 f x /2 11 f x /2 5 selector selector coincidence mask circuit ovf clear 3 selector tcl22 tcl21 tcl20 timer clock select register 2 (tcl2) internal bus tce2 tmc26 lvs2 lvr2 tmc21 toe2 invert level timer mode control register 2 (tmc2) s r s q r inv selector inttm2 tio2/p43 f x /2 3 f x /2 7 f x /2 8 f x /2 9 p43 output latch pm43 note
120 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 figure 9-2. timer 3 (tm3) block diagram note bit 4 of port mode register 4 (pm4) internal bus 8-bit compare register 3 (cr3) 8-bit counter 3 (tm3) tio3/p44 f x /2 12 f x /2 4 f x /2 6 selector coincidence mask circuit ovf clear 3 selector tcl32 tcl31 tcl30 timer clock select register 3 (tcl3) internal bus tce3 tmc36 lvs3 lvr3 tmc31 toe3 invert level timer mode control register 3 (tmc3) s r q r inv selector inttm3 s tio3/p44 p44 output latch pm44 note f x /2 7 f x /2 8 f x /2 10 selector
121 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 9.2 8-bit timer/event counters 2 and 3 configurations timers 2 and 3 consist of the following hardware. table 9-1. timers 2 and 3 configurations item configuration timer register 8-bit counter n (tmn) register 8-bit compare register n (crn) timer output 2 (tion) control register timer clock select register n (tcln) 8-bit timer mode control register n (tmcn) remark n = 2, 3 (1) 8-bit counter n (tmn: n = 2, 3) tmn is an 8-bit read-only register which counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. when count value is read during operation, count clock input is temporary stopped, and then the count value is read. in the following situations, the count value is set to 00h. <1> reset input <2> clear tcen <3> match between tmn and crn in clear and start made with match between tmn and crn remark n = 2, 3 (2) 8-bit compare register n (crn: n = 2, 3) the value set in the crn is constantly compared with the 8-bit counter n (tmn) count value, and an interrupt request (inttmn) is generated if they match (except pwm mode). it is possible to rewrite the value of crn within 00h to ffh during count operation. remark n = 2, 3
122 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 9.3 8-bit timer/event counters 2 and 3 control registers the following two types of registers are used to control timers 2 and 3. ? timer clock select register n (tcln) ? 8-bit timer mode control register n (tmcn) n = 2, 3 (1) timer clock select register n (tcln: n = 2, 3) this register sets count clocks of timers 2 and 3. tcln is set with an 8-bit memory manipulation instruction. reset input sets to 00h. figure 9-3. timer clock select register 2 (tcl2) format address: ff74h after reset: 00h r/w symbol 76543210 tcl2 00000 tcl22 tcl21 tcl20 tcl22 tcl21 tcl20 count clock selection 0 0 0 tio2 falling edge 0 0 1 tio2 rising edge 010f x /2 3 (1.04 mhz) 011f x /2 5 (261 khz) 100f x /2 7 (65.4 khz) 101f x /2 8 (32.7 khz) 110f x /2 9 (16.3 khz) 111f x /2 11 (4.09 khz) cautions 1. when rewriting tcl2 to other data, stop the timer operation beforehand. 2. set bits 3 to 7 to 0. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.38 mhz
123 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 figure 9-4. timer clock select register 3 (tcl3) format address: ff75h after reset: 00h r/w symbol 76543210 tcl3 00000 tcl32 tcl31 tcl30 tcl32 tcl31 tcl30 count clock selection 0 0 0 tio3 falling edge 0 0 1 tio3 rising edge 010f x /2 4 (523 khz) 011f x /2 6 (130 khz) 100f x /2 7 (65.4 khz) 101f x /2 8 (32.7 khz) 110f x /2 10 (8.18 khz) 111f x /2 12 (2.04 khz) cautions 1. when rewriting tcl3 to other data, stop the timer operation beforehand. 2. set bits 3 to 7 to 0. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.38 mhz (2) 8-bit timer mode control register n (tmcn: n = 2, 3) tmcn is a register which sets up the following five types. <1> 8-bit counter n (tmn) count operation control <2> 8-bit counter n (tmn) operating mode selection <3> timer output f/f (flip flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode. <5> timer output control tmcn is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets to 04h. figure 9-5 shows tmcn format.
124 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 figure 9-5. 8-bit timer mode control register n (tmcn) format address: ff77h (tmc2) ff78h (tmc3) after reset: 04h r/w symbol 76543210 tmcn tcen tmcn6 0 0 lvsn lvrn tmcn1 toen tcen tm2, tm3 count operation control 0 after clearing counter to 0, count operation disabled (prescaler disabled) 1 count operation start tmcn6 tm2, tm3 operating mode selection 0 clear and start mode by matching between tmn and crn 1 pwm (free-running) mode lvsn lvrn timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (to 0) 1 0 timer output f/f set (to 1) 1 1 setting prohibited tmcn1 in other modes (tmcn6 = 0) in pwm mode (tmcn6 = 1) timer f/f control active level selection 0 inversion operation disabled active high 1 inversion operation enabled active low toen timer output control 0 output disabled (port mode) 1 output enabled cautions 1. set bit 4 and bit 5 to 0. 2. bit 2 and bit 3 are write-only. remarks 1. in pwm mode, pwm output will be inactive because of tcen = 0. 2. if lvsn and lvrn are read after data is set, they will be 0. 3. n = 2, 3
125 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 9.4 8-bit timer/event counters 2 and 3 operations 9.4.1 8-bit interval timer operation the 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare register n (crn). when the count values of the 8-bit counter n (tmn) match the values set to crn, counting continues with the tmn values cleared to 0 and the interrupt request signal (inttmn) is generated. count clock of the tmn can be selected with bits 0 to 2 (tcln0 to tcln2) of the timer clock select register n (tcln). [setting] <1> set the registers. ? tcln : select count clock. ? crn : compare value ? tmcn : select clear and start mode by match of tmn and crn. (tmcn = 0000 0b = dont care) <2> after tcen = 1 is set, count operation starts. <3> if the values of tmn and crn match, the inttmn is generated and tmn is cleared to 00h. <4> inttmn generates repeatedly at the same interval. set tcen to 0 to stop count operation. remark n = 2, 3 figure 9-6. interval timer operation timings (1/3) (a) basic operation t count clock tmn count value crn tcen inttmn tion start count clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt received interrupt received interval time interval time interval time remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. n = 2, 3
126 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 figure 9-6. interval timer operation timings (2/3) (b) when crn = 00h t count clock tmn crn tcen inttmn tion interval time 00h 00h 00h 00h 00h (c) when crn = ffh t count clock tmn crn tcen inttmn tion 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt received interrupt received n = 2 , 3
127 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 figure 9-6. interval timer operation timings (3/3) (d) operated by crn transition (m < n) count clock tmn crn tcen inttmn tion 00h n n m n ffh 00h m 00h m crn transition tmn overflows since m < n (e) operated by crn transition (m > n) count clock tmn crn tcen inttmn tion n? n n 00h 01h n m? m 00h 01h m crn transition n = 2, 3 9.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to the tion. tmn is incremented each time the valid edge specified with the timer clock select register n (tcln) is input. either the rising or falling edge can be selected. when the tmn counted values match the values of 8-bit compare register n (crn), tmn is cleared to 0 and the interrupt request signal (inttmn) is generated. whenever the tmn value matches the value of crn, inttmn is generated. remark n = 2, 3
128 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 figure 9-7. external event counter operation timings (with rising edge specified) tion tmn count value crn inttmn 0000 0001 0002 0003 0004 0005 n? n 0000 0001 0002 0003 n n = 2, 3 9.4.3 square-wave output operation (8-bit resolution) a square wave with any selected frequency is output at intervals of the value preset to 8-bit compare register n (crn). tion pin output status is inverted at intervals of the count value preset to crn by setting bit 0 (toen) of 8-bit timer mode control register n (tmcn) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). [setting] <1> set each register. ? set port latch and port mode register to 0. ? tcln: select count clock ? crn: compare value ? tmcn: clear and start mode by match of tmn and crn lvsn lvrn timer output f/f status setting 1 0 high-level output 0 1 low-level output timer output f/f inversion enabled timer output enabled ? toen = 1 <2> after tcen = 1 is set, count operation starts. <3> timer output f/f is inverted by match of tmn and crn. after inttmn is generated, tmn is cleared to 00h. <4> timer output f/f is inverted at the same interval and square wave is output from tion. remark n = 2, 3
129 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 9.4.4 8-bit pwm output operation 8-bit timer/event counters operate as pwm output when bit 6 (tmcn6) of 8-bit timer mode control register n (tmcn) is set to 1. the duty rate pulse determined by the value set to 8-bit compare register n (crn) is output from tion. set the active level width of pwm pulse to crn, and the active level can be selected with bit 1 (tmcn1) of tmcn. count clock can be selected with bit 0 to bit 2 (tcln0 to tcln2) of timer clock select register n (tcln). pwm output enable/disable can be selected with bit 0 (toen) of tmcn. caution rewrite of crn in pwm mode is allowed only once in a cycle. remark n = 2, 3 (1) pwm output basic operation [setting] <1> set port latch (p43, p44) and port mode register 4 (pm43, pm44) to 0. <2> set active level width with 8-bit compare register (crn). <3> select count clock with timer clock select register n (tcln). <4> set active level with bit 1 (tmcn1) of tmcn. <5> count operation starts when bit 7 (tcen) of tmcn is set to 1. set tcen to 0 to stop count operation. [pwm output operation] <1> pwm output (output from tion) outputs inactive level after count operation starts until overflow is generated. <2> when overflow is generated, the active level set in <1> of setting is output. the active level is output until crn matches the count value of 8-bit counter n (tmn). <3> after the crn matches the count value, pwm output outputs the inactive level again until overflow is generated. <4> pwm output operation <2> and <3> are repeated until the count operation stops. <5> when the count operation is stopped with tcen = 0, pwm output changes to inactive level. remark n = 2, 3
130 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 (a) pwm output basic operation figure 9-8. pwm output operation timing (i) basic operation (active level = h) count clock tmn crn tcen inttmn tion 00h 01h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h n active level active level inactive level (ii) crn = 0 count clock tmn crn tcen inttmn tion inactive level inactive level 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h 00h n+2 (iii) crn = ffh tmn crn tcen inttmn tion 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h ffh n+2 inactive level active level inactive level active level inactive level n = 2, 3
131 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 (b) operation by change of crn figure 9-9. timing of operation by change of crn (i) change of crn value to n to m before overflow of tmn count clock tmn crn tcen inttmn tion crn transition (n ? m) n n+1 n+2 ffh 00h 01h m m+1 m+2 ffh 00h 01h 02h m m+1 m+2 n 02h m h (ii) change of crn value to n to m after overflow of tmn count clock tmn crn tcen inttmn tion n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h 03h m m m+1 m+2 crn transition (n ? m) (iii) change of crn value to n to m between two clocks (00h and 01h) after overflow of tmn count clock tmn crn tcen inttmn tion n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h m m m+1 m+2 crn transition (n ? m) n = 2, 3
132 chapter 9 8-bit timer/event counters 2, 3 tm2, tm3 9.5 8-bit timer/event counters 2 and 3 cautions (1) timer start errors an error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. this is because 8-bit counter n (tmn) is started asynchronously with the count pulse. figure 9-10. timer n start timing count pulse tmn count value 00h 01h 02h 03h 04h timer start n = 2, 3 (2) operation after compare register change during timer count operation if the values after the 8-bit compare register n (crn) is changed are smaller than the value of 8-bit timer register n (tmn), tmn continues counting, overflows and then restarts counting from 0. thus, if the value (m) after crn change is smaller than value (n) before the change, it is necessary to restart the timer after changing crn. figure 9-11. timing after compare register change during timer count operation count pulse crn tmn count value nm x? x ffh 00h 01h 02h remarks 1. n > x > m 2. n = 2, 3 caution except when the tion input is selected, always set tcen = 0 before setting the stop state. remark n = 2, 3 (3) tmn (n = 2, 3) reading during timer operation when tmn is read during operation, choose a select clock which has a longer high/low level wave because the select clock is stopped temporarily.
133 chapter 10 watch timer 10.1 watch timer functions the watch timer has the following functions. ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. figure 10-1 shows watch timer block diagram. figure 10-1. watch timer block diagram 9-bit prescaler 5-bit counter selector selector selector wtm7 f x /2 7 f x /2 11 wtm6 wtm5 wtm4 internal bus wtm3 wtm1 wtm0 watch timer mode control register (wtm) clear clear intwt intwti f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f w
134 chapter 10 watch timer (1) watch timer when the main system clock is used, interrupt requests (intwt) are generated at 0.25 second (at f x = 8.38- mhz operation) intervals. (2) interval timer interrupt requests (intwt) are generated at the preset time interval. table 10-1. interval timer interval time interval time when operated at f x = 8.38 mhz 2 12 1/f x 489 m s 2 13 1/f x 978 m s 2 14 1/f x 1.96 ms 2 15 1/f x 3.91 ms 2 16 1/f x 7.82 ms 2 17 1/f x 15.65 ms remark f x : main system clock oscillation frequency 10.2 watch timer configuration the watch timer consists of the following hardware. table 10-2. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
135 chapter 10 watch timer 10.3 watch timer control register the watch timer mode control register (wtm) is used to control the watch timer. ? watch timer mode control register (wtm) this register sets the watch timer count clock, operation enable/disable, prescaler interval time and 5-bit counter operation control. wtm is set with an 8-bit memory manipulation instruction. reset input clears wtm to 00h. figure 10-2. watch timer mode control register (wtm) format address: ff41h after reset: 00h r/w symbol 76543210 wtm wtm7 wtm6 wtm5 wtm4 wtm3 0 wtm1 wtm0 wtm7 watch timer count clock selection 0f x /2 7 (65.4 khz) 1f x /2 11 (4.09 khz) wtm6 wtm5 wtm4 prescaler interval time selection 0002 4 /f w (3.91 ms) 0012 5 /f w (7.82 ms) 0102 6 /f w (15.6 ms) 0112 7 /f w (31.2 ms) 1002 8 /f w (62.5 ms) 1012 9 /f w (125 ms) other than above setting prohibited wtm3 watch flag set time selection 0 normal operating mode (flag set at f w /2 14 ) 1 fast feed operating mode (flag set at f w /2 5 ) wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer operation control 0 operation stop (clear both prescaler and timer) 1 operation enable remarks 1. f w : watch timer clock frequency (f x /2 7 or f x /2 11 ) 2. f x : main system clock oscillation frequency 3. figures in parentheses apply to operation with f x = 8.38 mhz, f w = 4.09 khz.
136 chapter 10 watch timer 10.4 watch timer operations 10.4.1 watch timer operation when the 8.38-mhz main system clock is used, the timer operates as a watch timer with a 0.25-second interval. the watch timer generates interrupt requests at a constant time interval. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer mode control register are set to 1, the count operation starts. when set to 0, the 5-bit counter is cleared and the count operation stops. for simultaneous operation of the interval timer, zero-second start can be set only for the watch timer by setting wtm1 to 0. however, since the 9-bit prescaler is not cleared the first overflow of the watch timer (intwt) after zero- second start may include an error of up to 2 9 1/f w . 10.4.2 interval timer operation the watch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm4 to wtm6) of the watch timer mode control register (wtm). table 10-3. interval timer interval time wtm6 wtm5 wtm4 interval time when operated at when operated at f w = 65.4 khz f w = 4.09 khz 00 02 4 1/f w 244 m s 3.91 ms 00 12 5 1/f w 489 m s 7.81 ms 01 02 6 1/f w 978 m s 15.6 ms 01 12 7 1/f w 1.96 ms 31.3 ms 10 02 8 1/f w 3.91 ms 62.5 ms 10 12 9 1/f w 7.82 ms 125 ms other than above setting prohibited remark f w : watch timer clock frequency
137 chapter 10 watch timer figure 10-3. operation timing of watch timer/interval timer 0h start overflow overflow 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.25 s) interval timer (t) t interrupt time of watch timer (0.25 s) remark f w : watch timer clock frequency ( ) : f w = 4.09 khz (f x = 8.38 mhz)
138 [memo]
139 chapter 11 watchdog timer 11.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (wdtm). figure 11-1 shows the watchdog timer block diagram. figure 11-1. watchdog timer block diagram prescaler intwdt maskable interrupt request intwdt non-maskable interrupt request reset wdtif wdtmk run selector control circuit f x /2 7 f x /2 12 f x /2 13 f x /2 14 f x /2 15 f x /2 16 f x /2 17 f x /2 18 f x /2 20 3 internal bus internal bus wdcs2 wdcs1 wdcs0 run wdtm4 wdtm3 watchdog timer mode register (wdtm) watchdog timer clock select register (wdcs)
140 chapter 11 watchdog timer (1) watchdog timer mode a runaway is detected. upon detection of the runaway, a non-maskable interrupt request or reset can be generated. table 11-1. watchdog timer runaway detection time runaway detection time 2 12 1/f x (489 m s) 2 13 1/f x (978 m s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.38 mhz. (2) interval timer mode interrupt requests are generated at preset time intervals. table 11-2. interval time interval time 2 12 1/f x (489 m s) 2 13 1/f x (978 m s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.38 mhz.
141 chapter 11 watchdog timer 11.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 11-3. watchdog timer configuration item configuration control register watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) 11.3 watchdog timer control registers the following two types of registers are used to control the watchdog timer. ? watchdog timer clock select register (wdcs) ? watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) this register sets overflow time of the watchdog timer and the interval timer. wdcs is set with an 8-bit memory manipulation instruction. reset input clears wdcs to 00h. figure 11-2. watchdog timer clock select register (wdcs) format address: ff42h after reset: 00h r/w symbol 76543210 wdcs 00000 wdcs2 wdcs1 wdcs0 wdcs2 wdcs1 wdcs0 overflow time of watchdog timer/interval timer 0002 12 /f x (489 m s) 0012 13 /f x (978 m s) 0102 14 /f x (1.96 ms) 0112 15 /f x (3.91 ms) 1002 16 /f x (7.82 ms) 1012 17 /f x (15.6 ms) 1102 18 /f x (31.3 ms) 1112 20 /f x (125 ms) cautions 1. when rewriting wdcs to other data, stop the timer operation beforehand. 2. bits 3 to 7 must be set to 0. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.38 mhz
142 chapter 11 watchdog timer (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 11-3. watchdog timer mode register (wdtm) format address: fff9h after reset: 00h r/w symbol 76543210 wdtm run 0 0 wdtm4 wdtm3 0 0 0 run watchdog timer operation mode selection note 1 0 count stop 1 counter is cleared and counting starts wdtm4 wdtm3 watchdog timer operation mode selection note 2 0 interval timer mode (maskable interrupt request occurs upon generation of an overflow) 1 0 watchdog timer mode 1 (non-maskable interrupt request occurs upon generation of an overflow) 1 1 watchdog timer mode 2 (reset operation is activated upon generation of an overflow) notes 1. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. 2. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. cautions 1. when 1 is set in run so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the watchdog timer clock select register. 2. to use watchdog timer modes 1 and 2, make sure that the interrupt request flag (wdtif) is 0, and then set wdtm4 to 1. if wdtm4 is set to 1 when wdtif is 1, the non-maskable interrupt request occurs, regardless of the contents of wdtm3. remark : dont care
143 chapter 11 watchdog timer 11.4 watchdog timer operations 11.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect any runaways. watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set runaway time interval. the watchdog timer can be cleared and counting is started. if run is not set to 1 and the runaway detection time is past, system reset or a non-maskable interrupt request is generated according to the wdtm bit 3 (wdtm3) value. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. caution the actual runaway detection time may be shorter than the set time by a maximum of 0.5%. table 11-4. watchdog timer runaway detection time runaway detection time 2 12 1/f x (489 m s) 2 13 1/f x (978 m s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.38 mhz.
144 chapter 11 watchdog timer 11.4.2 interval timer operation the watchdog timer operates as an interval timer which generates interrupt request repeatedly at an interval of the preset count value when bit 3 (wdtm3) and bit 4 (wdtm4) of the watchdog timer mode register (wdtm) are set to 1 and 0, respectively. when the watchdog timer operates as interval timer, the interrupt mask flag (wdtmk) and priority specify flag (wdtpr) are validated and the maskable interrupt request (intwdt) can be generated. among maskable interrupts, the intwdt default has the highest priority. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set run to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless reset input is applied. 2. the interval time just after setting with wdtm may be shorter than the set time by a maximum of 0.5%. table 11-5. interval timer interval time interval time 2 12 1/f x (489 m s) 2 13 1/f x (978 m s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.38 mhz.
145 chapter 12 clock output control circuit 12.1 clock output control circuit functions the clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsis. the clock selected with the clock output selection register (cks) is output from the pcl/sgoa/p60 pin. figure 12-1 shows the clock output control circuit (cku) block diagram. figure 12-1. clock output control circuit block diagram f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 selector clock control circuit cloe ccs2 ccs1 ccs0 pm60 pcl/sgoa/p60 clock output selection register (cks) port mode register 6 (pm6) p60 output latch 3 internal bus sgoa note note sgoa: sound generator amplitude signal 12.2 clock output control circuit configuration the clock output control circuit (cku) consists of the following hardware. table 12-1. clock output control circuit configuration item configuration control register clock output selection register (cks) port mode register 6 (pm6)
146 chapter 12 clock output control circuit 12.3 clock output control circuit control registers the following two types of registers are used to control the cku. ? clock output selection register (cks) ? port mode register 6 (pm6) (1) clock output selection register (cks) this register sets output clock. cks is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears cks to 00h. figure 12-2. clock output selection register (cks) format address: ff40h after reset: 00h r/w symbol 76543210 cks 0 0 0 cloe 0 ccs2 ccs1 ccs0 cloe pcl output enable/disable specification 0 stop clock division circuit operation. 1 enable clock division circuit operation. ccs2 ccs1 ccs0 pcl output clock selection 000f x (8.38 mhz) 001f x /2 (4.19 mhz) 010f x /2 2 (2.09 mhz) 011f x /2 3 (1.04 mhz) 100f x /2 4 (524 khz) 101f x /2 5 (262 khz) 110f x /2 6 (131 khz) 111f x /2 7 (65.5 khz) cautions 1. when rewriting cks to other data, stop the timer operation beforehand. 2. bit 3 and bits 5 to 7 must be set to 0. remarks 1. f x = main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.38 mhz.
147 chapter 12 clock output control circuit (2) port mode register 6 (pm6) this register sets port 6 input/output in 1-bit units. when using the p60/pcl/sgoa pin for clock output, set pm60 and the output latch of p60 to 0. pm6 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm6 to ffh. figure 12-3. port mode register 6 (pm6) format address: ff26h after reset: ffh r/w symbol 76543210 pm6 111111 pm61 pm60 pm6n p6n pin input/output mode selection (n = 0 , 1) 0 output mode (output buffer on) 1 input mode (output buffer off)
148 chapter 12 clock output control circuit 12.4 clock output control circuit operation 12.4.1 clock output operation to output the clock pulse, follow the procedure described below. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the clock output selection register (cks) (clock pulse output in disabled status). <2> set bit 3 (sgob) of the sound generator control register (sgcr) to 1 (sgof output in disabled status). <3> set the p60 output latch to 0. <4> set bit 0 (pm60) of port mode register 6 to 0 (set to output mode). <5> set bit 4 (cloe) of cks to 1, and enable clock output. remark the clock output control circuit is designed not to output pulses with a small width during output enable/ disable switching of the clock output. as shown in figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure below). when stopping output, do so after securing high level of the clock. figure 12-4. remote control output application example cloe clock output **
149 chapter 13 a/d converter 13.1 a/d converter functions the a/d converter is an 8-bit resolution converter that converts analog inputs into digital values. it can control up to 5 analog input channels (ani0 to ani4). this a/d converter has the following functions: (1) a/d conversion with 8-bit resolution one channel of analog input is selected from ani0 to ani4, and a/d conversion is repeatedly executed with a resolution of 8 bits. each time the conversion has been completed, interrupt request (intad) is generated. (2) power-fail detection function this function is to detect a voltage drop in the battery of an automobile. the result of a/d conversion (value of the adcr1 register) and the value of pft register (pft: power-fail compare threshold value register) are compared. if the condition for comparison is satisfied, intad is generated. figure 13-1. a/d converter block diagram ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 selector sample & hold circuit voltage comparator successive approximation register (sar) control circuit 3 a/d conversion result register (adcr1) tap selector av ref av ss intad a/d converter mode register analog input channel specification register internal bus ads12 ads11 ads10 adcs1 fr12 fr11 fr10
150 chapter 13 a/d converter figure 13-2. power-fail detection function block diagram ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 multiplexer selector a/d converter internal bus power-fail compare mode register (pfm) comparator pfen pfcm power-fail compare threshold value register (pft) intad pfen pfcm 13.2 a/d converter configuration a/d converter consists of the following hardware. table 13-1. a/d converter configuration item configuration analog input 5 channels (ani0 to ani4) register successive approximation register (sar) a/d conversion result register (adcr1) control register a/d converter mode register (adm1) analog input channel specification register (ads1) power-fail compare mode register (pfm) power-fail compare threshold value register (pft) (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is set (end of a/d conversion), the sar contents are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr1) this register holds the a/d conversion result. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. adcr1 is read with an 8-bit memory manipulation instruction. reset input clears adcr1 to 00h. caution when write operation is executed to a/d converter mode register (adm1) and analog input channel specification register (ads1), the contents of adcr1 are undefined. read the conversion result before write operation is executed to adm1, ads1. if a timing other than the above is used, the correct conversion result may not be read.
151 chapter 13 a/d converter (3) sample & hold circuit the sample & hold circuit samples each analog input sequentially applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is in av ref to av ss , and generates a voltage to be compared to the analog input. (6) ani0 to ani4 pins these are five analog input pins to input analog signals to undergo a/d conversion to the a/d converter. ani0 to ani4 are alternate-function pins that can also be used for digital input. caution use ani0 to ani4 input voltages within the specification range. if a voltage higher than av ref or lower than av ss is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (7) av ref pin (shared with av dd pin) this pin inputs the a/d converter reference voltage. this pin also functions as an analog power supply pin. supply power to this pin when the a/d converter is used. it converts signals input to ani0 to ani4 into digital signals according to the voltage applied between av ref and av ss . the current flowing in the series resistor string can be reduced by setting the voltage to be input to the av ref pin to av ss level in the standby mode. (8) av ss pin this is the gnd potential pin of the a/d converter. always keep it at the same potential as the v ss pin even when not using the a/d converter.
152 chapter 13 a/d converter 13.3 a/d converter control registers the following 4 types of registers are used to control a/d converter. ? a/d converter mode register (adm1) ? analog input channel specification register (ads1) ? power-fail compare mode register (pfm) ? power-fail compare threshold value register (pft) (1) a/d converter mode register (adm1) this register sets the conversion time for analog input to be a/d converted, conversion start/stop and external trigger. adm1 is set with an 8-bit memory manipulation instruction. reset input clears adm1 to 00h. figure 13-3. a/d converter mode register (adm1) format address: ff80h after reset: 00h r/w symbol 76543210 adm1 adcs1 0 fr12 fr11 fr10 0 0 0 adcs1 a/d conversion operation control 0 stop conversion operation. 1 enable conversion operation. fr12 fr11 fr10 conversion time selection note 0 0 0 144/f x 0 0 1 120/f x 0 1 0 96/f x 1 0 0 288/f x 1 0 1 240/f x 1 1 0 192/f x other than above setting prohibited note set so that the a/d conversion time is 19.1 m s or more. caution bits 0 to 2 and bit 6 must be set to 0. remark f x : main system clock oscillation frequency
153 chapter 13 a/d converter (2) analog input channel specification register (ads1) this register specifies the analog voltage input port for a/d conversion. ads1 is set with an 8-bit memory manipulation instruction. reset input clears ads1 to 00h. figure 13-4. analog input channel specification register (ads1) format address: ff81h after reset: 00h r/w symbol 76543210 ads1 00000 ads12 ads11 ads10 ads12 ads11 ads10 analog input channel specification 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 other than above setting prohibited caution bits 3 to 7 must be set to 0.
154 chapter 13 a/d converter (3) power-fail compare mode register (pfm) the power-fail compare mode register (pfm) controls a comparison operation. reset input clears pfm to 00h. figure 13-5. power-fail compare mode register (pfm) format address: ff82h after reset: 00h r/w symbol 76543210 pfm pfen pfcm 000000 pfen enables power-fail comparison 0 disables power-fail comparison (used as normal a/d converter) 1 enables power-fail comparison (used to detect power failure) pfcm power-fail compare mode selection 0 adcr1 pft generates interrupt request signal intad adcr1 < pft does not generate interrupt request signal intad 1 adcr1 pft does not generate interrupt request signal intad adcr1 < pft generates interrupt request signal intad caution bits 0 to 5 must be set to 0. (4) power-fail compare threshold value register (pft) the power-fail compare threshold value register (pft) sets a threshold value against which the result of a/d conversion is to be compared. pft is set with an 8-bit memory manipulation instruction. reset input clears pft to 00h.
155 chapter 13 a/d converter 13.4 a/d converter operations 13.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with the analog input channel specification register (ads1). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> set bit 7 of the successive approximation register (sar) so that the tap selector sets the series resistor string voltage tap to (1/2) av ref . <5> the voltage difference between the series resistor string voltage tap and analog input is compared with the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set. if the analog input is smaller than (1/2) av ref , the msb is reset. <6> next, bit 6 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 7, as described below. ? bit 7 = 1: (3/4) av ref ? bit 7 = 0: (1/4) av ref the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 6 = 1 ? analog input voltage < voltage tap: bit 6 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 8 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in the a/d conversion result register (adcr1). at the same time, the a/d conversion end interrupt request (intad) can also be generated.
156 chapter 13 a/d converter figure 13-6. basic operation of 8-bit a/d converter conversion time sampling time sampling a/d conversion undefined 80h c0h or 40h conversion result a/d converter operation sar adcr1 intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs1) of the a/d converter mode register (adm1) is reset (to 0) by software. if a write operation to the adm1 and analog input channel specification register (ads1) is performed during an a/d conversion operation, the conversion operation is initialized, and if the adcs1 bit is set (to 1), conversion starts again from the beginning. reset input sets the a/d conversion result register (adcr1) to 00h.
157 chapter 13 a/d converter 13.4.2 input voltage and conversion results the relation between the analog input voltage input to the analog input pins (ani0 to ani4) and the a/d conversion result (stored in the a/d conversion result register (adcr1)) is shown by the following expression. adcr1 = int ( v in 256 + 0.5) av ref or (adcr1 C 0.5) av ref v in < (adcr1 + 0.5) av ref 256 256 where, int( ) : function which returns integer part of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr1 : a/d conversion result register (adcr1) value figure 13-7 shows the relation between the analog input voltage and the a/d conversion result. figure 13-7. relation between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr1) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av ref
158 chapter 13 a/d converter 13.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one analog input channel is selected from among ani0 to ani4 with the analog input channel specification register (ads1) and a/d conversion is performed. the following two types of functions can be selected by setting the pfen flag of the pfm register. (1) normal 8-bit a/d converter (pfen = 0) (2) power-fail detection function (pfen = 1) (1) a/d conversion (when pfen = 0) when bit 7 (adcs1) of the a/d converter mode register (adm1) is set to 1 and bit 7 of the power-fail compare mode register (pfm) is set to 0, a/d conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ads1) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr1), and the interrupt request signal (intad) is generated. after one a/d conversion operation is started and ended, the next conversion operation is immediately started. a/d conversion operations are repeated until new data is written to ads1. if ads1 is rewritten during a/d conversion operation, the a/d conversion operation under execution is stopped, and a/d conversion of a newly selected analog input channel is started. if data with adcs1 set to 0 is written to adm1 during a/d conversion operation, the a/d conversion operation stops immediately. (2) power-fail detection function (when pfen = 1) when bit 7 (adcs1) of the a/d converter mode register (adm1) and bit 7 (pfen) of the power-fail compare mode register (pfm) are set to 1, a/d conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ads1) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr1), compared with the value of the power-fail compare threshold value register (pft), and intad is generated under the condition specified by the pfcm flag of the pfm register. caution when executing power-fail comparison, the interrupt request signal (intad) is not gener- ated on completion of the first conversion after adcs1 has been set to 1. intad is valid from completion of the second conversion.
159 chapter 13 a/d converter figure 13-8. a/d conversion adm1 rewrite adcs1 = 1 ads1 rewrite adcs1 = 0 a/d conversion adcr1 intad (pfen = 0) intad (pfen = 1) anin anin anin anim anim stop anin anin anim conversion suspended; conversion results are not stored first conversion condition satisfied remarks 1. n = 0, 1, ..., 4 2. m = 0, 1, ..., 4
160 chapter 13 a/d converter 13.5 a/d converter cautions (1) current consumption in standby mode a/d converter stops operating in the standby mode. at this time, current consumption can be reduced by setting bit 7 (adcs1) of the a/d converter mode register (adm1) to 0 to stop conversion. figure 13-9 shows how to reduce the current consumption in the standby mode. figure 13-9. example of method of reducing current consumption in standby mode av ref av ss p-ch series resistor string adcs1 (2) input range of ani0 to ani4 the input voltages of ani0 to ani4 should be within the specification range. in particular, if a voltage higher than av ref or lower than av ss is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations <1> contention between a/d conversion result register (adcr1) write and adcr1 read by instruction upon the end of conversion adcr1 read is given priority. after the read operation, the new conversion result is written to adcr1. <2> contention between adcr1 write and a/d converter mode register (adm1) write or analog input channel specification register (ads1) write upon the end of conversion adm1 or ads1 write is given priority. adcr1 write is not performed, nor is the conversion end interrupt request signal (intad) generated.
161 chapter 13 a/d converter (4) noise countermeasures to maintain 8-bit resolution, attention must be paid to noise input to pin av ref and pins ani0 to ani4. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 13-10 to reduce noise. figure 13-10. analog input pin connection reference voltage input c = 100 to 1000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani4 (5) ani0 to ani4 the analog input pins (ani0 to ani4) also function as input port pins (p10 to p14). when a/d conversion is performed with any of pins ani0 to ani4 selected, do not execute a port input instruction while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) av ref pin input impedance a series resistor string of approximately 21 k w is connected between the av ref pin and the av ss pin. therefore, if the output impedance of the reference voltage is high, this will result in parallel connection to the series resistor string between the av ref pin and the av ss pin, and there will be a large reference voltage error.
162 chapter 13 a/d converter (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel specification register (ads1) is changed. caution is therefore required since, if a change of analog input pin is performed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads1 rewrite, and when adif is read immediately after the ads1 rewrite, adif may be set despite the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is stopped and then resumed, clear adif before the a/d conversion operation is resumed. figure 13-11. a/d conversion end interrupt request generation timing ads1 rewrite (start of anin conversion) a/d conversion adcr1 intad anin anin anim anim anin anin anim anim ads1 rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0, 1, ..., 4 2. m = 0, 1, ..., 4 (8) read of a/d conversion result register (adcr1) when write operation is executed to a/d converter mode register (adm1) and analog input channel specification register (ads1), the contents of adcr1 are undefined. read the conversion result before write operation is executed to adm1, ads1. if a timing other than the above is used, the correct conversion result may not be read.
163 chapter 13 a/d converter 13.6 cautions on emulation (1) d/a converter mode register (dam1) to perform debugging with an in-circuit emulator (ie-78k0-ns), the d/a converter mode register (dam1) must be set. dam1 is a register used to set a probe board (ie-780974-ns-em1). dam1 is used when the power-fail detection function is used. unless dam1 is set, the power-fail detection function cannot be used. dam1 is a write-only register. because the ie-780974-ns-em1 uses an external analog comparator and a d/a converter to implement part of the power-fail detection function, the reference voltage must be controlled. therefore, set bit 0 (dace) of dam1 to 1 when using the power-fail detection function. figure 13-12. d/a converter mode register (dam1) format address: ff89h after reset: 00h w symbol 76543210 dam1 0000000 dace dace reference voltage control 0 disabled 1 enabled (when power-fail detection function is used) cautions 1. dam1 is a special register that must be set when debugging is performed with an in-circuit emulator. even if this register is used, the operation of the m pd780973 subseries is not affected. however, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. bits 7 to 1 must be set to 0. (2) a/d converter of ie-780974-ns-em1 the a/d converter of the ie-780974-ns-em1 may not satisfy the rating of the first a/d conversion value right after a/d conversion has been started. the above applies only to the ie-780974-ns-em1 and does not affect the operation of the m pd780973 subseries.
164 [memo]
165 chapter 14 serial interface uart 14.1 uart functions the serial interface uart has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. for details, see 14.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data is transmitted and received after the start bit. the on-chip dedicated uart baud rate generator enables communications using a wide range of selectable baud rates. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). for details, see 14.4.2 asynchronous serial interface (uart) mode . figure 14-1 shows the uart block diagram. figure 14-1. uart block diagram internal bus internal bus receive buffer register (rxb) receive shift register (rxs) direction control circuit direction control circuit transmit control circuit baud rate generator transmit shift register (txs) receive control circuit 3 34 asynchronous serial interface status register (asis) asynchronous serial interface mode register (asim) baud rate generator control register (brgc) rxd/p53 txd/p54 intser intsr txe intst txe rxe ps1 ps0 cl sl isrm tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 fe pe ove f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 selector f sck
166 chapter 14 serial interface uart 14.2 uart configuration the uart consists of the following hardware. table 14-1. uart configuration item configuration registers transmit shift register (txs) receive shift register (rxs) receive buffer register (rxb) control registers asynchronous serial interface mode register (asim) asynchronous serial interface status register (asis) baud rate generator control register (brgc) (1) transmit shift register (txs) this is the register for setting transmit data. data written to txs is transmitted as serial data. when the data length is set as 7 bits, bits 0 to 6 of the data written to txs are transmitted as transmit data. writing data to txs starts the transmit operation. txs is written with an 8-bit memory manipulation instruction. it cannot be read. when reset is input, its value is ffh. caution do not write to txs during a transmit operation. the same address is assigned to txs and the receive buffer register (rxb). a read operation reads values from rxb. (2) receive shift register (rxs) this register converts serial data input via the rxd pin to parallel data. when one byte of data is received at this register, the receive data is transferred to the receive buffer register (rxb). rxs cannot be manipulated directly by a program. (3) receive buffer register (rxb) this register is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred from the receive shift register (rxs). when the data length is set as 7 bits, receive data is transferred to bits 0 to 6 of rxb. in rxb, the msb must be set to 0. rxb is read with an 8-bit memory manipulation instruction. it cannot be written to. when reset is input, its value is ffh. caution the same address is assigned to rxb and the transmit shift register (txs). during a write operation, values are written to txs. (4) transmit control circuit the transmit control circuit controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to the transmit shift register (txs), based on the values set to the asynchronous serial interface mode register (asim).
167 chapter 14 serial interface uart (5) receive control circuit the receive control circuit controls receive operations based on the values set to the asynchronous serial interface mode register (asim). during a receive operation, it performs error checking, such as for parity errors, and sets various values to the asynchronous serial interface status register (asis) according to the type of error that is detected. 14.3 uart control registers the uart uses the following three types of registers for control functions. ? asynchronous serial interface mode register (asim) ? asynchronous serial interface status register (asis) ? baud rate generator control register (brgc) (1) asynchronous serial interface mode register (asim) this is an 8-bit register that controls uarts serial transfer operations. asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears the value to 00h. figure 14-2 shows the format of asim. caution in uart mode, set the port mode register (pm5x) as follows. besides that, set all output latches to 0. ? when receiving set p53 (r x d) to the input mode (pm53 = 1) ? when transmitting set p54 (t x d) to the output mode (pm54 = 0) ? when transceiving set p53 to the input mode and p54 to the output mode
168 chapter 14 serial interface uart figure 14-2. asynchronous serial interface mode register (asim) format address: ff85h after reset: 00h r/w symbol 76543210 asim txe rxe ps1 ps0 cl sl isrm 0 txe rxe operation mode 0 0 operation stop 0 1 uart mode (receive only) 1 0 uart mode (transmit only) 1 1 uart mode (transmit and receive) ps1 ps0 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl character length specification 0 7 bits 1 8 bits sl stop bit length specification for transmit data 0 1 bit 1 2 bits isrm receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs cautions 1. do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. bit 0 must be set to 0.
169 chapter 14 serial interface uart (2) asynchronous serial interface status register (asis) when a receive error occurs during uart mode, this register indicates the type of error. asis is read with an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 14-3. asynchronous serial interface status register (asis) format address: ff86h after reset: 00h r symbol 76543210 asis 00000pefeove pe parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fe framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if a stop bit length of two bits has been set to bit 2 (sl) in the asynchronous serial interface mode register (asim), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb) when an overrun error has occurred. until the contents of rxb are read, further overrun errors will occur when receiving data. (3) baud rate generator control register (brgc) this register sets the serial clock for uart. brgc is set with an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 14-4 shows the format of brgc.
170 chapter 14 serial interface uart figure 14-4. baud rate generator control register (brgc) format address: ff87h after reset: 00h r/w symbol 76543210 brgc 0 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 (f x = 8.38 mhz) tps2 tps1 tps0 source clock selection for 5-bit counter n 000f x /2 1 001f x /2 2 2 010f x /2 3 3 011f x /2 4 4 100f x /2 5 5 101f x /2 6 6 110f x /2 7 7 111f x /2 8 8 mdl3 mdl2 mdl1 mdl0 input clock selection for baud rate generator k 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibited cautions 1. writing to brgc during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc during a communication operation. 2. bit 7 must be set to 0. remarks 1. f sck : source clock for 5-bit counter 2. n : value set via tps0 to tps2 (1 n 8) 3. k : value set via mdl0 to mdl3 (0 k 14)
171 chapter 14 serial interface uart 14.4 uart operations this section explains the two modes of the uart. 14.4.1 operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. in the operation stop mode, p53/rxd and p54/txd pins can be used as ordinary ports. (1) register settings operation stop mode settings are made via the asynchronous serial interface mode register (asim). asim is set with a 1-bit or 8-bit memory manipulation instruction. when reset is input, its value is 00h. address: ff85h after reset: 00h r/w symbol 76543210 asim txe rxe ps1 ps0 cl sl isrm 0 txe rxe operation mode rxd/p53 pin function txd/p54 pin function 0 0 operation stop port function port function 0 1 uart mode serial function port function (receive only) 1 0 uart mode port function serial function (transmit only) 1 1 uart mode serial function serial function (transmit and receive) cautions 1. do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. bit 0 must be set to 0. 14.4.2 asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data is transmitted or received after the start bit. the on-chip dedicated uart baud rate generator enables communications using a wide range of selectable baud rates. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). (1) register settings uart mode settings are made via the asynchronous serial interface mode register (asim), asynchronous serial interface status register (asis), and the baud rate generator control register (brgc).
172 chapter 14 serial interface uart (a) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. when reset is input, its value is 00h. caution in uart mode, set the port mode register (pm5x) as follows. besides that, set all output latches to 0. ? when receiving set p53 (r x d) to the input mode (pm53 = 1) ? when transmitting set p54 (t x d) to the output mode (pm54 = 0) ? when transceiving set p53 to the input mode and p54 to the output mode address: ff85h after reset: 00h r/w symbol 76543210 asim txe rxe ps1 ps0 cl sl isrm 0 txe rxe operation mode rxd/p53 pin function txd/p54 pin function 0 0 operation stop port function port function 0 1 uart mode serial function port function (receive only) 1 0 uart mode port function serial function (transmit only) 1 1 uart mode serial function serial function (transmit and receive) ps1 ps0 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl character length specification 0 7 bits 1 8 bits sl stop bit length specification for transmit data 0 1 bit 1 2 bits isrm receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs cautions 1. do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. bit 0 must be set to 0.
173 chapter 14 serial interface uart (b) asynchronous serial interface status register (asis) asis is read with an 8-bit memory manipulation instruction. when reset is input, its value is 00h. address: ff86h after reset: 00h r symbol 76543210 asis 00000pefeove pe parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fe framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if a stop bit length of two bits has been set to bit 2 (sl) in the asynchronous serial interface mode register (asim), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb) when an overrun error has occurred. until the contents of rxb are read, further overrun errors will occur when receiving data.
174 chapter 14 serial interface uart (c) baud rate generator control register (brgc) brgc is set with an 8-bit memory manipulation instruction. when reset is input, its value is 00h. address: ff87h after reset: 00h r/w symbol 76543210 brgc 0 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 (f x = 8.38 mhz) tps2 tps1 tps0 source clock selection for 5-bit counter n 000f x /2 1 001f x /2 2 2 010f x /2 3 3 011f x /2 4 4 100f x /2 5 5 101f x /2 6 6 110f x /2 7 7 111f x /2 8 8 mdl3 mdl2 mdl1 mdl0 input clock selection for baud rate generator k 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibited cautions 1. writing to brgc during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. there- fore, do not write to brgc during a communication operation. 2. bit 7 must be set to 0. remarks 1. f sck : source clock for 5-bit counter 2. n : value set via tps0 to tps2 (1 n 8) 3. k : value set via mdl0 to mdl3 (0 k 14)
175 chapter 14 serial interface uart the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. ? use of main system clock to generate a transmit/receive clock for baud rate the main system clock is divided to generate the transmit/receive clock. the baud rate generated by the main system clock is determined according to the following formula. [baud rate] = f x [hz] 2 n+1 (k + 16) f x : main system clock oscillation frequency n : value set via tps0 to tps2 (1 n 8) for details, see table 14-2. k : value set via mdl0 to mdl3 (0 k 14) table 14-2 shows the relation between the 5-bit counters source clock assigned to bits 4 to 6 (tps0 to tps2) of brgc and the n value in the above formula. table 14-2. relation between 5-bit counters source clock and n value tps2 tps1 tps0 5-bit counters source clock selection n 000f x /2 1 001f x /2 2 2 010f x /2 3 3 011f x /2 4 4 100f x /2 5 5 101f x /2 6 6 110f x /2 7 7 111f x /2 8 8 remark f x : main system clock oscillation frequency (f x = 8.38 mhz)
176 chapter 14 serial interface uart error tolerance range for baud rates the tolerance range for baud rates depends on the number of bits per frame and the counters division rate [1/(16 + k)]. table 14-3 describes the relation between the main system clock and the baud rate and figure 14-5 shows an example of a baud rate error tolerance range. table 14-3. relation between main system clock and baud rate baud rate f x = 8.386 mhz (bps) brgc set value error (%) 600 7bh 1.10 1200 6bh 1.10 2400 5bh 1.10 4800 4bh 1.10 9600 3bh 1.10 19200 2bh C1.3 31250 21h 1.10 38400 1bh 1.10 76800 0bh 1.10 115200 01h 1.03 remark f x : main system clock oscillation frequency figure 14-5. error tolerance (when k = 0) including sampling errors basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t? enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t? enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t remark t : 5-bit counters source clock cycle baud rate error tolerance (when k = 0) = 15.5 100 = 4.8438 (%) 320
177 chapter 14 serial interface uart (2) communication operations (a) data format as shown in figure 14-6, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. the asynchronous serial interface mode register (asim) is used to set the character bit length, parity selection, and stop bit length within each data frame. figure 14-6. format of transmit/receive data in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame ? start bit ............. 1 bit ? character bits ... 7 bits or 8 bits ? parity bit ........... even parity, odd parity, zero parity, or no parity ? stop bit(s) ........ 1 bit or 2 bits when 7 bits is selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to 0. the asynchronous serial interface mode register (asim) and the baud rate generator control register (brgc) are used to set the serial transfer rate. if a receive error occurs, information about the receive error can be recognized by reading the asynchronous serial interface status register (asis).
178 chapter 14 serial interface uart (b) parity types and operations the parity bit is used to detect bit errors in transfer data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. when zero parity or no parity is set, errors are not detected. (i) even parity ? during transmission the number of bits in transmit data that includes a parity bit is controlled so that there are an even number of 1 bits. the value of the parity bit is as follows. if the transmit data contains an odd number of 1 bits : the parity bit value is 1 if the transmit data contains an even number of 1 bits: the parity bit value is 0 ? during reception the number of 1 bits is counted among the receive data that include a parity bit, and a parity error occurs when the result is an odd number. (ii) odd parity ? during transmission the number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of 1 bits. the value of the parity bit is as follows. if the transmit data contains an odd number of 1 bits : the parity bit value is 0 if the transmit data contains an even number of 1 bits: the parity bit value is 1 ? during reception the number of 1 bits is counted among the receive data that include a parity bit, and a parity error occurs when the result is an even number. (iii) zero parity during transmission, the parity bit is set to 0 regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will occur regardless of whether the parity bit is a 0 or a 1. (iv) no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will occur.
179 chapter 14 serial interface uart (c) transmission the transmit operation is started when transmit data is written to the transmit shift register (txs). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting the transmit operation shifts out the data in txs, thereby emptying txs, after which a transmit completion interrupt (intst) is issued. the timing of the transmit completion interrupt is shown in figure 14-7. figure 14-7. timing of asynchronous serial interface transmit completion interrupt txd (output) d0 d1 d2 d6 d7 parity stop start intst (i) stop bit length: 1 bit txd (output) d0 d1 d2 d6 d7 parity start intst (ii) stop bit length: 2 bits stop caution do not rewrite the asynchronous serial interface mode register (asim) during a transmit operation. rewriting to the asim register during a transmit operation may disable further transmit operations (in such case, enter a reset to restore normal operation). whether or not a transmit operation is in progress can be determined by software using the transmit completion interrupt (intst) or the interrupt request flag (stif) that is set by intst.
180 chapter 14 serial interface uart (d) reception the receive operation is enabled when 1 is set to bit 6 (rxe) of the asynchronous serial interface mode register (asim), and input via the rxd pin is sampled. the serial clock specified by asim is used when sampling the rxd pin. when the rxd pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. if sampling the rxd pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once reception of one data frame is completed, the receive data in the shift register is transferred to the receive buffer register (rxb) and a receive completion interrupt (intsr) occurs. even if an error has occurred, the receive data in which the error occurred is still transferred to rxb. intsr occurs if bit 1 (isrm) of asim is cleared to 0 on occurrence of an error. if the isrm bit is set to 1, intsr does not occur (see figure 14-9). if the rxe bit is reset (to 0) during a receive operation, the receive operation is stopped immediately. at this time, the contents of rxb and asis do not change, nor does intsr or intser occur. figure 14-8 shows the timing of the asynchronous serial interface receive completion interrupt. figure 14-8. timing of asynchronous serial interface receive completion interrupt rxd (input) d0 d1 d2 d6 d7 parity stop start intsr caution be sure to read the contents of the receive buffer register (rxb) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb are read.
181 chapter 14 serial interface uart (e) receive errors three types of errors can occur during a receive operation: parity error, framing error, or overrun error. if, as the result of data reception, an error flag is set to the asynchronous serial interface status register (asis), a receive error interrupt (intser) will occur. receive error interrupts are generated before receive interrupts (intsr). table 14-4 lists the causes behind receive errors. as part of receive error interrupt (intser) servicing, the contents of asis can be read to determine which type of error occurred during the receive operation (see table 14-4 and figure 14-9). the contents of asis are reset (to 0) when the receive buffer register (rxb) is read or when the next data is received (if the next data contains an error, another error flag will be set). table 14-4. causes of receive errors receive error cause asis value parity error parity specified during transmission does not match parity of receive data 04h framing error stop bit was not detected 02h overrun error reception of the next data was completed before data was read from the 01h receive buffer register figure 14-9. receive error timing rxd (input) d0 d1 d2 d6 d7 parity stop start intsr note intser (when framing/overrun error occurs) intser (when parity error occurs) note if a reception error occurs when bit 1 (isrm) of the asynchronous serial interface mode register (asim) is set to 1, intsr does not occur. cautions 1. the contents of asynchronous serial interface status register (asis) are reset (to 0) when the receive buffer register (rxb) is read or when the next data is received. to obtain information about the error, be sure to read the contents of asis before reading rxb. 2. be sure to read the contents of the receive buffer register (rxb) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb are read.
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183 chapter 15 serial interface sio3 15.1 sio3 functions the serial interface sio3 has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. for details, see 15.4.1 operation stop mode . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck), serial output line (so), and serial input line (si). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit in the 8-bit data in serial transfers is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clock-synchronous serial interface, a display controller, etc. for details, see 15.4.2 three-wire serial i/o mode . figure 15-1 shows the sio3 block diagram. figure 15-1. sio3 block diagram internal bus internal bus selector serial i/o shift register (sio) serial clock counter serial clock control circuit intcsi serial operation mode register (csim) 2 si/p52 so/p51 sck/p50 csie mode scl1 scl0 f x /2 2 f x /2 3 f x /2 4
184 chapter 15 serial interface sio3 15.2 sio3 configuration the sio3 consists of the following hardware. table 15-1. sio3 configuration item configuration register serial i/o shift register (sio) control register serial operation mode register (csim) (1) serial i/o shift register (sio) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sio is set with an 8-bit memory manipulation instruction. when 1 is set to bit 7 (csie) of the serial operation mode register (csim), a serial operation can be started by writing data to or reading data from sio. when transmitting, data written to sio is output via the serial output (so). when receiving, data is read from the serial input (si) and written to sio. the reset signal resets the register value to 00h. caution do not access sio during a transfer operation unless the access is triggered by a transfer start (read is disabled when mode = 0 and write is disabled when mode = 1).
185 chapter 15 serial interface sio3 15.3 sio3 control register the sio3 uses the following type of register for control functions. ? serial operation mode register (csim) (1) serial operation mode register (csim) this register is used to enable or disable sio3s serial clock, operation modes, and specific operations. csim is set with a 1-bit or 8-bit memory manipulation instruction. the reset input resets the value to 00h. caution in the 3-wire serial i/o mode, set the port mode register (pm5x) as follows. besides that, set all output latches to 0. ? when serial clock output (master transmit or master receive) set p50 (sck) to the output mode (pm50 = 0) ? when serial clock input (slave transmit or slave receive) set p50 to the input mode (pm50 = 1) ? when transmit/transceive mode set p51 (so) to the output mode (pm51 = 0) ? when receive mode set p52 (si) to the input mode (pm52 = 1) figure 15-2. serial operation mode register (csim) format address: ff84h after reset: 00h r/w symbol 76543210 csim csie 0000 mode scl1 scl0 csie sio3 operation enable/disable specification shift register operation 0 operation disable 1 operation enable mode transfer operation mode flag operation mode 0 transmit or transmit/receive mode 1 receive-only mode scl1 scl0 clock selection (f x = 8.38 mhz) 0 0 external clock input 01f x /2 2 10f x /2 3 11f x /2 4 caution bits 3 to 6 must be set to 0.
186 chapter 15 serial interface sio3 15.4 sio3 operations this section explains the two modes of the sio3. 15.4.1 operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. in the operation stop mode, the p50/sck, p51/so, and p52/si pins can be used as normal i/o ports as well. (1) register settings operation stop mode are set via serial operation mode register (csim). csim is set with a 1-bit or 8-bit memory manipulation instruction. the reset input resets the value to 00h. figure 15-3. serial operation mode register (csim) format address: ff84h after reset: 00h r/w symbol 76543210 csim csie 0000 mode scl1 scl0 csie sio3 operation enable/disable specification shift register operation 0 operation disable 1 operation enable caution bits 3 to 6 must be set to 0.
187 chapter 15 serial interface sio3 15.4.2 three-wire serial i/o mode the three-wire serial i/o mode is useful when connecting a peripheral i/o device that includes a clock-synchronous serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sck), serial output line (so), and serial input line (si). (1) register settings 3-wire serial i/o mode is set via serial operation mode register (csim). csim is set with a 1-bit or 8-bit memory manipulation instruction. the reset input resets the value to 00h. caution in the 3-wire serial i/o mode, set the port mode register (pm5x) as follows. besides that, set all output latches to 0. ? when serial clock output (master transmit or master receive) set p50 (sck) to the output mode (pm50 = 0) ? when serial clock input (slave transmit or slave receive) set p50 to the input mode (pm50 = 1) ? when transmit/transceive mode set p51 (so) to the output mode (pm51 = 0) ? when receive mode set p52 (si) to the input mode (pm52 = 1) figure 15-4. serial operation mode register (csim) format address: ff84h after reset: 00h r/w symbol 76543210 csim csie 0000 mode scl1 scl0 csie sio3 operation enable/disable specification shift register operation 0 operation disable 1 operation enable mode transfer operation mode flag operation mode 0 transmit or transmit/receive mode 1 receive-only mode scl1 scl0 clock selection (f x = 8.38 mhz) 0 0 external clock input 01f x /2 2 10f x /2 3 11f x /2 4 caution bits 3 to 6 must be set to 0.
188 chapter 15 serial interface sio3 (2) communication operations in the three-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is transmitted or received in synchronized with the serial clock. the serial i/o shift register (sio) is shifted in synchronized with the falling edge of the serial clock. transmission data is held in the so latch and is output from the so pin. data that is received via the si pin in synchronized with the rising edge of the serial clock is latched to sio. completion of an 8-bit transfer automatically stops operation of sio3 and sets a serial transfer completion flag. figure 15-5. three-wire serial i/o mode timing si di7 di6 di5 di4 di3 di2 di1 di0 serial transfer completion flag serial clock 1 so do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronized with the serial clock? falling edge (3) transfer start a serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial i/o shift register (sio). ? sio3 operation control bit (csie) = 1 ? after an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. ? transmit or transmit/receive mode when csie = 1 and mode = 0, transfer starts when writing to sio. ? receive-only mode when csie = 1 and mode = 1, transfer starts when reading from sio. caution after data has been written to sio, transfer will not start even if the csie bit value is set to 1. completion of an 8-bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag.
189 chapter 16 lcd controller/driver 16.1 lcd controller/driver functions the functions of the lcd controller/driver incorporated in the m pd780973 subseries are shown below. (1) automatic output of segment signals and common signals is possible by automatic reading of the display data memory. (2) display mode ? 1/4 duty (1/3 bias) (3) any of four frame frequencies can be selected in each display mode. (4) maximum of 20 segment signal outputs (s0 to s19); 4 common signal outputs (com0 to com3). fifteen of the segment signal outputs can be switched to input/output ports in units of 2 (p81/s19 to p87/s13, p90/s12 to p97/s5). the maximum number of displayable pixels is shown in table 16-1. table 16-1. maximum number of display pixels bias method time division common signals used maximum number of display pixels 1/3 4 com0 to com3 80 (20 segments 4 commons) note note 10 digits on type lcd panel with 2 segments/digit.
190 chapter 16 lcd controller/driver 16.2 lcd controller/driver configuration the lcd controller/driver consists of the following hardware. table 16-2. lcd controller/driver configuration item configuration display outputs segment signals : 20 dedicated segment signals: 5 segment signal/input/output port alternate function: 14 segment signal/input/output port/16-bit timer prescaler output alternate function: 1 common signals : 4 (com0 to com3) control registers lcd display mode register (lcdm) lcd display control register (lcdc) figure 16-1. lcd controller/driver block diagram internal bus fa59h 7 6 5 4 3 2 1 0 fa67h 7 6 5 4 3 2 1 0 fa68h 7 6 5 4 3 2 1 0 fa6ch 7 6 5 4 3 2 1 0 display data memory 3 2 1 0 selector 3 2 1 0 selector 3 2 1 0 selector 3 2 1 0 selector ??? ??? note note note note p97 output buffer s4 s0 ??? ??? ????? ??? s5/p97 p81 output buffer s19/p81 segment selector common driver com0 com3 com1 com2 lcd driver voltage controller v lcd lcdon lcdm6 lcdm5 lcdm4 lcd clock selector f lcd 3 lcd display mode register (lcdm) lcdc6 lcdc5 lcdc4 lips lcd display control register (lcdc) 4 ?????? ??? timing controller lcdc7 note segment driver
191 chapter 16 lcd controller/driver figure 16-2. lcd clock select circuit block diagram prescaler f lcd /2 3 f x /2 14 f lcd /2 2 f lcd /2 f lcd selector lcdm6 lcdm5 lcdm4 3 lcdcl lcd display mode register internal bus remarks 1. lcdcl : lcd clock 2. f lcd : lcd clock frequency
192 chapter 16 lcd controller/driver 16.3 lcd controller/driver control registers the lcd controller/driver is controlled by the following two registers. ? lcd display mode register (lcdm) ? lcd display control register (lcdc) (1) lcd display mode register (lcdm) this register sets display operation enabling/disabling, the lcd clock, frame frequency. lcdm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears lcdm to 00h. figure 16-3. lcd display mode register (lcdm) format address: ffb0h after reset: 00h r/w symbol 76543210 lcdm lcdon lcdm6 lcdm5 lcdm4 0000 lcdon lcd display enable/disable 0 display off (all segment outputs are non-select signal outputs) 1 display on lcdm6 lcdm5 lcdm4 lcd clock selection (f x = 8.38 mhz) 000f x /2 17 (64 hz) 001f x /2 16 (128 hz) 010f x /2 15 (256 hz) 011f x /2 14 (512 hz) other than above setting prohibited remark f x = main system clock oscillation frequency
193 chapter 16 lcd controller/driver (2) lcd display control register (lcdc) this register sets cutoff of the current flowing to split resistors for lcd drive voltage generation and switchover between segment output and input/output port functions. lcdc is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears lcdc to 00h. figure 16-4. lcd display control register (lcdc) format address: ffb2h after reset: 00h r/w symbol 76543210 lcdc lcdc7 lcdc6 lcdc5 lcdc4 0 0 0 lips lcdc7 lcdc6 lcdc5 lcdc4 p81/s19 to p97/s5 pin functions port pins segment pins 0 0 0 0 p81 to p97 none 0 0 0 1 p81 to p95 s5 to s6 0 0 1 0 p81 to p93 s5 to s8 0 0 1 1 p81 to p91 s5 to s10 0 1 0 0 p81 to p87 s5 to s12 0 1 0 1 p81 to p85 s5 to s14 0 1 1 0 p81 to p83 s5 to s16 0 1 1 1 p81 s5 to s18 1 0 0 0 none s5 to s19 other than above setting prohibited lips lcd driving power supply selection 0 does not supply power to lcd. 1 supplies power to lcd from v dd pin. cautions 1. pins which perform segment output cannot be used as output port pins even if 0 is set in the port mode register. 2. if a pin which performs segment output is read as a port, its value will be 0.
194 chapter 16 lcd controller/driver 16.4 lcd controller/driver settings lcd controller/driver settings should be performed as shown below. <1> set the initial value in the display data memory (fa59h to fa6ch). <2> set the pins to be used as segment outputs in the lcd display control register (lcdc). <3> set the lcd clock in the lcd display mode register (lcdm). next, set data in the display data memory according to the display contents.
195 chapter 16 lcd controller/driver 16.5 lcd display data memory the lcd display data memory is mapped onto addresses fa59h to fa6ch. the data stored in the lcd display data memory can be displayed on an lcd panel by the lcd controller/driver. figure 16-5 shows the relationship between the lcd display data memory contents and the segment outputs/ common outputs. any area not used for display can be used as normal ram. figure 16-5. relationship between lcd display data memory contents and segment/common outputs s0 fa6ch s1 fa6bh s2 fa6ah s3 fa69h s17/p83 fa5bh s18/p82 fa5ah s19/p81 fa59h com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address caution the higher 4 bits of the lcd display data memory do not incorporate memory. be sure to set them to 0.
196 chapter 16 lcd controller/driver 16.6 common signals and segment signals an individual pixel on an lcd panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the lcd drive voltage v lcd ). the light goes off when the potential difference becomes v lcd or lower. as an lcd panel deteriorates if a dc voltage is applied in the common signals and segment signals, it is driven by ac voltage. (1) common signals for common signals, the selection timing order is as shown in table 16-3, and operations are repeated with these as the cycle. table 16-3. com signals com signal time division 4-time division com0 com1 com2 com3 (2) segment signals segment signals correspond to a 20-byte lcd display data memory (fa59h to fa6ch). each display data memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the com0, com1, com2 and com3 timings respectively, and if the value of the bit is 1, it is converted to the selection voltage. if the value of the bit is 0, it is converted to the non-selection voltage and output to a segment pin (s0 to s19) (s18 to s5 have an alternate function as input/output port pins). consequently, it is necessary to check what combination of front surface electrodes (corresponding to the segment signals) and rear surface electrodes (corresponding to the common signals) of the lcd panel to be used form the display pattern, and then write bit data corresponding on a one-to-one basis with the pattern to be displayed. bits 4 to 7 are fixed at 0. (3) common signal and segment signal output waveforms the voltages shown in table 16-4 are output in the common signals and segment signals. the v lcd on voltage is only produced when the common signal and segment signal are both at the selection voltage; other combinations produce the off voltage. table 16-4. lcd drive voltage segment select level non-select level common v ss1 , v lc0 v lc1 , v lc2 select level v lc0 , v ss1 Cv lcd , +v lcd C1/3v lcd , +1/3v lcd non-select level v lc2 , v lc1 C1/3v lcd , +1/3v lcd C1/3v lcd , +1/3v lcd
197 chapter 16 lcd controller/driver figure 16-6 shows the common signal waveform, and figure 16-7 shows the common signal and segment signal voltages and phases. figure 16-6. common signal waveform t f = 4 x t comn (divided by 4) v lc0 v ss v lcd v lc1 v lc2 t: one lcdcl cycle t f : frame frequency figure 16-7. common signal and segment signal voltages and phases selected not selected common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1 t : one lcdcl cycle
198 chapter 16 lcd controller/driver 16.7 supplying lcd drive voltage v lc0 , v lc1 , and v lc2 the m pd780973 subseries have a split resistor to create an lcd drive voltage, and the drive voltage is fixed to 1/3 bias. to supply various lcd drive voltages, internal v dd or external v lcd supply voltage can be selected. table 16-5. lcd drive voltage bias method 1/3 bias method lcd drive voltage v lc0 v lcd v lc1 2/3 v lcd v lc2 1/3 v lcd figure 16-8 shows an example of supplying an lcd drive voltage from an internal source according to table 16-5. by using variable resistors r 1 and r 2 , a non-stepwise lcd drive voltage can be supplied.
199 chapter 16 lcd controller/driver figure 16-8. example of connection of lcd drive power supply (a) to supply lcd drive voltage from v dd v dd v ss v lcd = v dd p-ch lips (= 1) r r r v ss v lc2 v lc1 v lc0 v lcd open v lcd pin (b) to supply lcd drive voltage from external source v dd v lcd v dd r 1 r 2 v ss v ss v lcd = v dd p-ch lips (= 0) r r r v ss v lc2 v lc1 v lc0 v lcd 3r r 2 3r r 2 + 3r r 1 + r 1 r 2
200 chapter 16 lcd controller/driver 16.8 display mode 16.8.1 4-time-division display example figure 16-10 shows the connection of a 4-time-division type 10-digit lcd panel with the display pattern shown in figure 16-9 with the m pd780973 subseries segment signals (s0 to s19) and common signals (com0 to com3). the display example is 1234567890, and the display data memory contents (addresses fa59h to fa6ch) correspond to this. an explanation is given here taking the example of the 5th digit 6 ( ). in accordance with the display pattern in figure 16-9, selection and non-selection voltages must be output to pins s8 and s9 as shown in table 16-6 at the com0 to com3 common signal timings. table 16-6. selection and non-selection voltages (com0 to com3) segment s8 s9 common com0 s s com1 ns s com2 s s com3 ns s s: selection, ns: non-selection from this, it can be seen that 0101 must be prepared in the display data memory (address fa64h) corresponding to s8. examples of the lcd drive waveforms between s8 and the com0 and com1 signals are shown in figure 16- 11 (for the sake of simplicity, waveforms for com2 and com3 have been omitted). when s8 is at the selection voltage at the com0 selection timing, it can be seen that the +v lcd /Cv lcd ac square wave, which is the lcd illumination (on) level, is generated. figure 16-9. 4-time-division lcd display pattern and electrode connections com0 s 2n com1 s 2n + 1 com2 com3 n = 0 to 9
201 chapter 16 lcd controller/driver figure 16-10. 4-time-division lcd panel connection example timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 s3 1 1 0 fa6ch 1 1 1 b 1 1 0 a 1 0 0 9 s4 s5 s6 s7 1 1 0 8 1 1 1 7 1 1 0 6 1 0 0 5 s8 s9 s10 s11 1 1 0 4 1 1 1 3 1 1 0 2 1 0 1 1 s12 s13 s14 s15 0 1 0 0 1 0 0 fa5fh 1 1 0 e 0 0 1 d s16 s17 s18 s19 1 0 0 c 0 1 1 b 0 1 0 a 0 0 0 fa59h data memory address lcd panel 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0
202 chapter 16 lcd controller/driver figure 16-11. 4-time-division lcd drive waveform examples (1/3 bias method) t f v lc0 v lc2 com0 +v lcd 0 com0 to s8 ev lcd v lc1 +1/3v lcd e1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1 to s8 ev lcd +1/3v lcd e1/3v lcd v lc0 v lc2 s8 v lc1 v ss
203 chapter 16 lcd controller/driver 16.9 cautions on emulation (1) lcd timer control register (lcdtm) to perform debugging with an in-circuit emulator (ie-78k0-ns), the lcd timer control register (lcdtm) must be set. lcdtm is a register used to set a probe board (ie-780974-ns-em1). lcdtm is a write-only register that controls supply of the lcd clock. unless lcdtm is set, the lcd controller/ driver does not operate. therefore, set bit 1 (tmc21) of lcdtm to 1 when using the lcd controller/driver. figure 16-12. lcd timer control register (lcdtm) format address: ff4ah after reset: 00h w symbol 76543210 lcdtm 000000 tmc21 0 tmc21 lcd clock supply control 0 lcd controller/driver stop mode (supply of lcd clock is stopped) 1 lcd controller/driver operating mode (supply of lcd clock is enabled) cautions 1. lcdtm is a special register that must be set when debugging is performed with an in-circuit emulator. even if this register is used, the operation of the m pd780973 subseries is not affected. however, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. bits 7 to 2, and bit 0 must be set to 0.
204 [memo]
205 chapter 17 sound generator 17.1 sound generator function the sound generator has the function to sound the buzzer from an external speaker, and the following two signals are output. (1) basic cycle output signal (with/without amplitude) the signal is a buzzer signal with a variable frequency. by setting bits 0 to 2 (sgcl0 to sgcl2) of the sound generator control register (sgcr), the signal in a range of 0.25 to 7.7 khz can be output (when f x = 8.38 mhz). the amplitude of the basic cycle output signal can be varied by anding the basic cycle output signal with the 7-bit-resolution pwm signal, to enable control of the buzzer sound volume. (2) amplitude output signal a pwm signal with a 7-bit resolution for variable amplitude can be independently output. figure 17-1 shows the sound generator block diagram and figure 17-2 shows the concept of each signal. figure 17-1. sound generator block diagram internal bus internal bus sound generator control register (sgcr) tce sgob sgcl2 sgcl1 sgcl0 2 4 7 q f x f sg1 f sg2 1/2 1/2 selector prescaler selector selector 5-bit counter comparator comparator sgo/sgof/p61 pcl/sgoa/p60 clear pwm amplitude s r sgob sgcl0 sgbr3 sgbr2 sgbr1 sgbr0 sgam6 sgam5 sgam4 sgam3 sgam2 sgam1 sgam0 p60 output latch clock output control circuit (pcl) pm60 sound generator buzzer control register (sgbr) sound generator amplitude register (sgam) port mode register 6 (pm6)
206 chapter 17 sound generator figure 17-2. concept of each signal basic cycle output sgof (without amplitude) amplitude output sgoa basic cycle output sgo (with amplitude) 17.2 sound generator configuration the sound generator consists of the following hardware. table 17-1. sound generator configuration item configuration counter 8 bits 1, 5 bits 1 sg output sgo/sgof (with/without append bit of basic cycle output) sgoa (amplitude output) control register sound generator control register (sgcr) sound generator buzzer control register (sgbr) sound generator amplitude register (sgam)
207 chapter 17 sound generator 17.3 sound generator control registers the following three types of registers are used to control the sound generator. ? sound generator control register (sgcr) ? sound generator buzzer control register (sgbr) ? sound generator amplitude register (sgam) (1) sound generator control register (sgcr) sgcr is a register which sets up the following four types. ? controls sound generator output ? selects output of sound generator ? selects sound generator input frequency f sg1 ? selects 5-bit counter input frequency f sg2 sgcr is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sgcr to 00h. figure 17-3 shows the sgcr format.
208 chapter 17 sound generator figure 17-3. sound generator control register (sgcr) format address: ff94h after reset: 00h r/w symbol 76543210 sgcr tce 0 0 0 sgob sgcl2 sgcl1 sgcl0 tce sound generator operation selection 0 timer operation stopped sgof/sgo and sgoa for low-level output 1 sound generator operation sgof/sgo and sgoa for output caution before setting the tce bit, set all the other bits. remark sgof: basic cycle signal (without amplitude) sgo: basic cycle signal (with amplitude) sgoa: amplitude signal sgob sound generator output selection 0 selects sgof and sgoa outputs 1 selects sgo and pcl outputs sgcl2 sgcl1 5-bit counter input frequency f sg2 selection 0 0 f sg2 = f sg1 /2 5 01f sg2 = f sg1 /2 6 10f sg2 = f sg1 /2 7 11f sg2 = f sg1 /2 8 sgcl0 sound generator input frequency selection 0f sg1 = f x /2 1f sg1 = f x cautions 1. when rewriting sgcr to other data, stop the timer operation (tce = 0) beforehand. 2. bits 4 to 6 must be set to 0.
209 chapter 17 sound generator the maximum and minimum values of the buzzer output frequency are as follows. sgcl2 sgcl1 sgcl0 maximum and minimum values of buzzer output f sg2 f x = 8 mhz f x = 8.38 mhz max. (khz) min. (khz) max. (khz) min. (khz) 000f sg1 /2 6 3.677 1.953 3.851 2.046 001f sg1 /2 5 7.354 3.906 7.702 4.092 010f sg1 /2 7 1.838 0.976 1.926 1.024 011f sg1 /2 6 3.677 1.953 0.481 2.046 100f sg1 /2 8 0.919 0.488 0.963 0.512 101f sg1 /2 7 1.838 0.976 1.926 1.024 110f sg1 /2 9 0.460 0.244 0.481 0.256 111f sg1 /2 8 0.919 0.488 0.963 0.512 the sound generator output frequency f sg can be calculated by the following expression. f sg = 2 (sgcl0 C sgcl1 C 2 sgcl2 C 7) {f x /(sgbr + 17)} substitute set 0 or 1 to sgcl0 to sgcl2 in the above expression. substitute a decimal value to sgbr. where f x = 8 mhz, sgcl0 to sgcl2 is (1, 0, 0), and sgbr0 to sgbr3 is (1, 1, 1, 1), sgbr = 15. therefore, f sg = 2 (1 C 0 C 2 0 C 7) {f x /(15 + 17)} = 3.906 khz (2) sound generator buzzer control register (sgbr) sgbr is a register that sets the basic frequency of the sound generator output signal. sgbr is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sgbr to 00h. figure 17-4 shows the sgbr format.
210 chapter 17 sound generator figure 17-4. sound generator buzzer control register (sgbr) format address: ff95h after reset: 00h r/w symbol 76543210 sgbr 0000 sgbr3 sgbr2 sgbr1 sgbr0 sgbr3 sgbr2 sgbr1 sgbr0 buzzer output frequency (khz) note f x = 8 mhz f x = 8.38 mhz 0 0 0 0 3.677 3.851 0 0 0 1 3.472 3.637 0 0 1 0 3.290 3.446 0 0 1 1 3.125 3.273 0 1 0 0 2.976 3.117 0 1 0 1 2.841 2.976 0 1 1 0 2.717 2.847 0 1 1 1 2.604 2.728 1 0 0 0 2.500 2.619 1 0 0 1 2.404 2.518 1 0 1 0 2.315 2.425 1 0 1 1 2.232 2.339 1 1 0 0 2.155 2.258 1 1 0 1 2.083 2.182 1 1 1 0 2.016 2.112 1 1 1 1 1.953 2.046 note output frequency where sgcl0, sgcl1, and sgcl2 are 0, 0, and 0. cautions 1. when rewriting sgbr to other data, stop the timer operation (tce = 0) beforehand. 2. bits 4 to 7 must be set to 0. (3) sound generator amplitude register (sgam) sgam is a register that sets the amplitude of the sound generator output signal. sgam is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sgam to 00h. figure 17-5 shows the sgam format.
211 chapter 17 sound generator figure 17-5. sound generator amplitude register (sgam) format address: ff96h after reset: 00h r/w symbol 76543210 sgam 0 sgam6 sgam5 sgam4 sgam3 sgam2 sgam1 sgam0 sgam6 sgam5 sgam4 sgam3 sgam2 sgam1 sgam0 amplitude 0 0 0 0 0 0 0 0/128 0 0 0 0 0 0 1 2/128 0 0 0 0 0 1 0 3/128 0 0 0 0 0 1 1 4/128 0 0 0 0 1 0 0 5/128 0 0 0 0 1 0 1 6/128 0 0 0 0 1 1 0 7/128 0 0 0 0 1 1 1 8/128 0 0 0 1 0 0 0 9/128 0 0 0 1 0 0 1 10/128 0 0 0 1 0 1 0 11/128 0 0 0 1 0 1 1 12/128 0 0 0 1 1 0 0 13/128 0 0 0 1 1 0 1 14/128 0 0 0 1 1 1 0 15/128 0 0 0 1 1 1 1 16/128 0 0 1 0 0 0 0 17/128 0 0 1 0 0 0 1 18/128 0 0 1 0 0 1 0 19/128 0 0 1 0 0 1 1 20/128 0 0 1 0 1 0 0 21/128 0 0 1 0 1 0 1 22/128 0 0 1 0 1 1 0 23/128 0 0 1 0 1 1 1 24/128 0 0 1 1 0 0 0 25/128 0 0 1 1 0 0 1 26/128 0 0 1 1 0 1 0 27/128 0 0 1 1 0 1 1 28/128 0 0 1 1 1 0 0 29/128 0 0 1 1 1 0 1 30/128 0 0 1 1 1 1 0 31/128 1 1 1 1 1 1 1 128/128 cautions 1. when rewriting the contents of sgam, the timer operation does not need to be stopped. however, note that a high level may be output for one period due to rewrite timing. 2. bit 7 must be set to 0. o o
212 chapter 17 sound generator 17.4 sound generator operations 17.4.1 to output basic cycle signal sgof (without amplitude) select sgof output by setting bit 3 (sgob) of the sound generator control register (sgcr) to 0. the basic cycle signal with a frequency specified by the sgcl0 to sgcl2 and sgbr0 to sgbr3 is output. at the same time, the amplitude signal with an amplitude specified by the sgam0 to sgam6 is output from the sgoa pin. figure 17-6. sound generator output operation timing timer comparator 1 coincidence sgof sgoa nnnnnn 17.4.2 to output basic cycle signal sgo (with amplitude) select sgo output by setting bit 3 (sgob) of the sound generator control register (sgcr) to 1. the basic cycle signal with a frequency specified by the sgcl0 to sgcl2 and sgbr0 to sgbr3 is output. when sgo output is selected, the sgoa pin can be used as a pcl output (clock output) or i/o port pin. figure 17-7. sound generator output operation timing timer comparator 1 coincidence sgof sgoa sgo nnnnnn
213 chapter 18 meter controller/driver 18.1 meter controller/driver functions the meter controller/driver is a function to drive a stepping motor for external meter control or cross coil. ? can set pulse width with a precision of 8 bits ? can set pulse width with a precision of 8 + 1 bits with 1-bit addition function ? can drive up to four 360? type meters figure 18-1 shows the block diagram of the meter controller/driver, figure 18-2 shows 1-bit addition circuit block diagram. figure 18-1. meter controller/driver block diagram remark n = 1 to 4 internal bus compare register (mcmpn0) 8-bit timer register f cc selector 1-bit addition circuit f x f x /2 pcs pce compare register (mcmpn1) 1-bit addition circuit internal bus modn enn port mode control register (pmc) timer mode control register (mcntc) dirn1 dirn0 adbn1 tenn adbn0 compare control register n (mcmpcn) output control circuit smn1 (sin+) smn2 (sin? modn ovf enn 2 2 q s r output control circuit smn3 (cos+) smn4 (cos? modn enn q s r
214 chapter 18 meter controller/driver figure 18-2. 1-bit addition circuit block diagram remark n = 1 to 4, m = 0, 1 18.2 meter controller/driver configuration the meter controller/driver consists of the following hardware. table 18-1. meter controller/driver configuration item configuration timer free-running up counter (mcnt): 1 channel register compare register (mcmpn1, mcmpn0): 8 channels control registers timer mode control register (mcntc) compare control register n (mcmpcn) port mode control register (pmc) pulse control circuit 1-bit addition circuit/output control circuit remark n = 1 to 4 (1) free running up counter (mcnt) mcnt is an 8-bit free running up counter, and is a register that executes increment at the rising edge of input clock. a pwm pulse with a resolution of 8 bits can be output. the duty factor can be set in a range of 0 to 100%. the count value is cleared in the following cases. ? when reset signal input ? when counter stops (pce = 0) cautions 1. mcnt executes counting operation from 01h to ffh repeatedly. however, it counts from 00h upon operation start. 2. the pwm output is not output until the first overflow of mcnt. internal bus f cc ovf compare register (mcmpnm) q s r q s selector adbn1 adbn0 compare control register (mcmpcn) 2
215 chapter 18 meter controller/driver (2) compare register n0 (mcmpn0) mcmpn0 is an 8-bit register that can rewrite compare values through specification of bit 4 (tenn) of the compare control register n (mcmpcn). reset input sets this register to 00h and clears hardware to 0. mcmpn0 is a register that supports read/write only for 8-bit access instructions. mcmpn0 continuously compares its value with the mcnt value. when the above two values match, a match signal of the sin side of meter n is generated. (3) compare register n1 (mcmpn1) mcmpn1 is an 8-bit register that can rewrite compare values through specification of bit 4 (tenn) of the compare control register n (mcmpcn). reset input sets this register to 00h and clears hardware to 0. mcmpn1 is a register that supports read/write only for 8-bit access instructions. mcmpn1 continuously compares its value with the mcnt value. when the above two values match, a match signal of the cos side of meter n is generated. (4) 1-bit addition circuit the 1-bit addition circuit repeats 1-bit addition/non-addition to pwm output alternately upon mcnt overflow output, and enables the state of pwm output between current compare value and the next compare value. this circuit is controlled by bits 2 and 3 (adbn0, adbn1) of the mcmpcn register. (5) output control circuit this circuit consists of a pch and nch drivers and can drive a meter in h bridge configuration by connecting a coil. when a meter is driven in half bridge configuration, the unused pins can be used as normal output port pins. the relation of the duty factor of the pwm signal output from the smnm pin is indicated by the following expression (n = 1 to 4, m = 0, 1). pwm (duty) = set value of mcmpnm cycle of mcnt count clock 100% 255 cycle of mcnt count clock = set value of mcmpnm 100% 255 cautions 1. mcmpn0 and mcmpn1 cannot be read or written by a 16-bit access instruction. 2. mcmpn0 and mcmpn1 are in master-slave configuration, and mcnt is compared with a slave register. the pwm pulse is not output until the first overflow occurs after the counting operation has been started because the compare data is not transferred to the slave.
216 chapter 18 meter controller/driver 18.3 meter controller/driver control registers the meter controller/driver is controlled by the following three registers. ? timer mode control register (mcntc) ? compare control register n (mcmpcn) ? port mode control register (pmc) remark n = 1 to 4 (1) timer mode control register (mcntc) mcntc is an 8-bit register that controls the operation of the free-running up counter (mcnt). mcntc is set with an 8-bit memory manipulation instruction. reset input clears mcntc to 00h. figure 18-3 shows the mcntc format. figure 18-3. timer mode control register (mcntc) format address: ff69h after reset: 00h r/w symbol 76543210 mcntc 0 0 pcs pce 0000 pcs timer counter clock selection 0f x 1f x /2 pce timer operation control 0 operation stopped (timer value is cleared) 1 operation enabled cautions 1. when rewriting mcntc to other data, stop the timer operation (pce = 0) beforehand. 2. bits 0 to 3, 6, and 7 must be set to 0.
217 chapter 18 meter controller/driver (2) compare control register (mcmpcn) mcmpcn is an 8-bit register that controls the operation of the compare register and output direction of the pwm pin. mcmpcn is set with an 8-bit memory manipulation instruction. reset input clears mcmpcn to 00h. figure 18-4 shows the mcmpcn format. figure 18-4. compare control register n (mcmpcn) format address: ff6bh to ff6eh after reset: 00h r/w symbol 76543210 mcmpcn (n = 1 to 4) 0 0 0 tenn adbn1 adbn0 dirn1 dirn0 tenn note enables transfer by register from master to slave 0 disables data transfer from master to slave. new data can be written. 1 transfer data from master to slave when mcnt overflows. new data cannot be written. adbn1 control of 1-bit addition circuit (cos side of meter n) 0 no 1-bit addition to pwm output 1 1-bit addition to pwm output adbn0 control of 1-bit addition circuit (sin side of meter n) 0 no 1-bit addition to pwm output 1 1-bit addition to pwm output note tenn functions as a control bit and status flag. as soon as the timer overflows and pwm data is output, tenn is cleared to 0 by hardware. the relation among the dirn1 and dirn0 bits of the mcmpcn register and output pin is shown below. dirn1 dirn0 direction control bit smn1 smn2 smn3 smn4 0 0 pwm 0 pwm 0 0 1 pwm 0 0 pwm 1 0 0 pwm 0 pwm 1 1 0 pwm pwm 0 caution bits 5 to 7 must be set to 0. (3) port mode control register (pmc) pmc is an 8-bit register that specifies pwm/port output. pmc is set with an 8-bit memory manipulation instruction. reset input clears pmc to 00h. figure 18-5 shows the pmc format.
218 chapter 18 meter controller/driver figure 18-5. port mode control register (pmc) format address: ff6ah after reset: 00h r/w symbol 76543210 pmc mod4 mod3 mod2 mod1 en4 en3 en2 en1 mod4 meter 4 full/half bridge selection 0 meter 4 output is full bridge. 1 meter 4 output is half bridge. mod3 meter 3 full/half bridge selection 0 meter 3 output is full bridge. 1 meter 3 output is half bridge. mod2 meter 2 full/half bridge selection 0 meter 2 output is full bridge. 1 meter 2 output is half bridge. mod1 meter 1 full/half bridge selection 0 meter 1 output is full bridge. 1 meter 1 output is half bridge. en4 meter 4 port/pwm mode selection 0 meter 4 output is in port mode. 1 meter 4 output is in pwm mode. en3 meter 3 port/pwm mode selection 0 meter 3 output is in port mode. 1 meter 3 output is in pwm mode. en2 meter 2 port/pwm mode selection 0 meter 2 output is in port mode. 1 meter 2 output is in pwm mode. en1 meter 1 port/pwm mode selection 0 meter 1 output is in port mode. 1 meter 1 output is in pwm mode.
219 chapter 18 meter controller/driver the relation among the enn and modn bits of the pmc register, dirn1 and dirn0 bits of the mcmpcn register, and output pins is shown below. enn modn dirn1 dirn0 smn1 smn2 smn3 smn4 mode (sin+) (sinC) (cos+) (cosC) 0 port port port port port mode 1 0 0 0 pwm 0 pwm 0 pwm mode full bridge 1 0 0 1 pwm 0 0 pwm 1 0 1 0 0 pwm 0 pwm 1 0 1 1 0 pwm pwm 0 1 1 0 0 pwm port pwm port pwm mode half bridge 1 1 0 1 pwm port port pwm 1 1 1 0 port pwm port pwm 1 1 1 1 port pwm pwm port dirn1 and dirn0 mean the quadrant of sin and cos, and dirn1, dirn0 = 00 through 11 correspond to quadrants 1 through 4, respectively. the pwm signal is output to the specific pin of the + and C polarities of sin and cos of each quadrant. when enn = 0, all the output pins are used as port pins regardless of modn, dirn1, and dirn0. when enn = 1 and modn = 0, the full bridge mode is set, and 0 is output to a pin that does not output a pwm signal. when enn = 1 and modn = 1, the half bridge mode is set, and the pin that does not output a pwm signal is used as a port pin. caution the output polarity of the pwm output changes when mcnt overflows.
220 chapter 18 meter controller/driver 18.4 meter controller/driver operations 18.4.1 basic operation of free-running up counter (mcnt) the free-running up counter is counted up by the count clock selected by the pcs bit of the timer mode control register. the value of mcnt is cleared by reset input. the counting operation is enabled or disabled by the pce bit of the timer mode control register (mcntc). figure 18-6 shows the timing from count start to restart. figure 18-6. restart timing after count stop (count start ? count stop ? count start) remark n = 00h to ffh 18.4.2 to update pwm data confirm that bit 4 (tenn) of mcmpcn is 0, and then set 8-bit pwm data to mcmpn1 and mcmpn0, and bits 2 and 3 (adbn1 and adbn0) of mcmpcn, and at the same time, set tenn to 1. the data will be automatically transferred to the slave latch when the timer overflows, and the pwm data becomes valid. at the same time, tenn is automatically cleared to 0. clk mcnt pce 0h 1h 2h 1h 2h 3h 4h n n + 1 00h ?? count start count stop count start
221 chapter 18 meter controller/driver 18.4.3 operation of 1-bit addition circuit figure 18-7. timing in 1-bit addition circuit operation the 1-bit addition mode repeats 1-bit addition/non-addition to pwm output alternately upon mcnt overflow output, and enables the state of pwm output between current compare value n and the next compare value n+1. in this mode, 1-bit addition to the pwm output is set by setting adbn of the mcmpcn register to 1, and 1-bit non-addition (normal output) is set by setting adbn to 0. remark n = 1 to 4 mcnt value ovf (overflow) match signal of expected value n pwm output of expected value n (1-bit non-addition) pwm output of expected value n (1-bit addition) pwm output of expected value n+1 (1-bit non-addition) ffh 00h 01h n
222 chapter 18 meter controller/driver 18.4.4 pwm output operation (output with 1 clock shifted) figure 18-8. timing of output with 1 clock shifted count clock meter 1 sin (sm11, sm12) meter 1 cos (sm13, sm14) meter 2 sin (sm21, sm22) meter 2 cos (sm23, sm24) meter 3 sin (sm31, sm32) meter 3 cos (sm33, sm34) meter 4 sin (sm41, sm42) meter 4 cos (sm43, sm44) if the wave of sin and cos of meters 1 to 4 rises and falls internally as indicated by the broken line, the sm11 to sm44 pins always shift the count clock by 1 clock and output signals, in order to prevent v dd /gnd from fluctuating.
223 chapter 19 interrupt functions 19.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even in the interrupt disabled state. it does not undergo priority control and is given top priority over all other interrupt requests. a standby release signal is generated. one interrupt request from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag registers (pr0l, pr0h, pr1l). multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (see table 19-1 ). a standby release signal is generated. three external interrupt requests and sixteen internal interrupt requests are incorporated as maskable interrupts. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in the interrupt disabled state. the software interrupt does not undergo interrupt priority control. 19.2 interrupt sources and configuration a total of 21 interrupt sources exist among non-maskable, maskable, and software interrupts (see table 19-1 ).
224 chapter 19 interrupt functions table 19-1. interrupt source list note 1 interrupt source internal/ vector basic interrupt type default external table configuration priority name trigger address type note 2 non-maskable intwdt watchdog timer overflow internal 0004h (a) (with non-maskable interrupt selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer selected) 1 intad end of a/d conversion 0006h 2 intovf 16-bit timer overflow 0008h 3 inttm00 ti00 valid edge detection 000ah (c) 4 inttm01 ti01 valid edge detection 000ch 5 inttm02 ti02 valid edge detection 000eh 6 intp0 pin input edge detection external 0010h (d) 7 intp1 0012h 8 intp2 0014h 9 intcsi end of serial interface sio3 transfer internal 0016h (b) 10 intser generation of serial interface uart receive error 0018h 11 intsr end of serial interface uart reception 001ah 12 intst end of serial interface uart transmission 001ch 13 inttm1 generation of 8-bit timer register and capture 001eh register (cr1) match signal 14 inttm2 generation of 8-bit timer register and capture 0020h register (cr2) match signal 15 inttm3 generation of 8-bit timer register and capture 0022h register (cr3) match signal 16 intwe end of eeprom write 0024h 17 intwti watch timer overflow 0026h 18 intwt reference time interval signal from watch timer 0028h software brk brk instruction execution 003eh (e) notes 1. the default priority is the priority applicable when two or more maskable interrupt requests are generated simultaneously. 0 is the highest priority, and 18 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 19-1.
225 chapter 19 interrupt functions figure 19-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (16-bit timer capture input) internal bus interrupt request priority control circuit vector table address generator standby release signal internal bus interrupt request if mk ie pr isp priority control circuit vector table address generator standb y release si g nal internal bus interrupt request if mk ie pr isp priority control circuit vector table address generator standby release signal sampling clock edge detector prescaler mode register (prm0)
226 chapter 19 interrupt functions figure 19-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (except 16-bit timer capture input) if mk ie pr isp internal bus interrupt request priority control circuit vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector (e) software interrupt internal bus interrupt request priority control circuit vector table address generator if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specify flag
227 chapter 19 interrupt functions 19.3 interrupt function control registers the following 7 types of registers are used to control the interrupt functions. ? interrupt request flag register (if0l, if0h, if1l) ? interrupt mask flag register (mk0l, mk0h, mk1l) ? priority specify flag register (pr0l, pr0h, pr1l) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? prescaler mode register (prm0) ? program status word (psw) table 19-2 gives a list of interrupt request flags, interrupt mask flags, and priority specify flags corresponding to interrupt request sources. table 19-2. flags corresponding to interrupt request sources interrupt source interrupt request flag interrupt mask flag priority specify flag register register register intwdt wdtif if0l wdtmk mk0l wdtpr pr0l intad adif admk adpr intovf ovfif ovfmk ovfpr inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 inttm02 tmif02 tmmk02 tmpr02 intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 if0h pmk2 mk0h ppr2 pr0h intcsi csiif csimk csipr intser serif sermk serpr intsr srif srmk srpr intst stif stmk stpr inttm1 tmif1 tmmk1 tmpr1 inttm2 tmif2 tmmk2 tmpr2 inttm3 tmif3 tmmk3 tmpr3 intwe weif if1l wemk mk1l wepr pr1l intwti wtiif wtimk wtipr intwt wtif wtmk wtpr remark the wdtif, wdtmk, and wdtpr flags are interrupt control flags when the watchdog timer is used as an interval timer.
228 chapter 19 interrupt functions (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, and if1l are set with a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h are combined to form 16-bit register if0, they are set with a 16-bit memory manipulation instruction. reset input sets these registers to 00h. figure 19-2. interrupt request flag register (if0l, if0h, if1l) format address: ffe0h after reset: 00h r/w symbol 76543210 if0l pif1 pif0 tmif02 tmif01 tmif00 ovfif adif wdtif address: ffe1h after reset: 00h r/w symbol 76543210 if0h tmif3 tmif2 tmif1 stif srif serif csiif pif2 address: ffe2h after reset: 00h r/w symbol 76543210 if1l 00000 wtif wtiif weif xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request signal is generated, interrupt request status cautions 1. the wdtif flag is r/w enabled only when the watchdog timer is used as the interval timer. if watchdog timer mode 1 is used, set the wdtif flag to 0. 2. be sure to set 0 to if1l bits 3 to 7.
229 chapter 19 interrupt functions (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt service. mk0l, mk0h, and mk1l are set with a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h are combined to form a 16-bit register mk0, they are set with a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 19-3. interrupt mask flag register (mk0l, mk0h, mk1l) format address: ffe4h after reset: ffh r/w symbol 76543210 mk0l pmk1 pmk0 tmmk02 tmmk01 tmmk00 ovfmk admk wdtmk address: ffe5h after reset: ffh r/w symbol 76543210 mk0h tmmk3 tmmk2 tmmk1 stmk srmk sermk csimk pmk2 address: ffe6h after reset: ffh r/w symbol 76543210 mk1l 11111 wtmk wtimk wemk xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled cautions 1. if the watchdog timer is used in watchdog timer mode 1, the contents of the wdtmk flag become undefined when read. 2. because port 0 pins have an alternate function as external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. be sure to set 1 to mk1l bits 3 to 7.
230 chapter 19 interrupt functions (3) priority specify flag registers (pr0l, pr0h, pr1l) the priority specify flag registers are used to set the corresponding maskable interrupt priority orders. pr0l, pr0h, and pr1l are set with a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are combined to form 16-bit register pr0, they are set with a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 19-4. priority specify flag register (pr0l, pr0h, pr1l) format address: ffe8h after reset: ffh r/w symbol 76543210 pr0l ppr1 ppr0 tmpr02 tmpr01 tmpr00 ovfpr adpr wdtpr address: ffe9h after reset: ffh r/w symbol 76543210 pr0h tmpr3 tmpr2 tmpr1 stpr srpr serpr csipr ppr2 address: ffeah after reset: ffh r/w symbol 76543210 pr1l 11111 wtpr wtipr wepr xxprx priority level selection 0 high priority level 1 low priority level cautions 1. when the watchdog timer is used in the watchdog timer mode 1, set 1 in the wdtpr flag. 2. be sure to set 1 to pr1l bits 3 to 7.
231 chapter 19 interrupt functions (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp2. egp and egn are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. figure 19-5. external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) format address: ff48h after reset: 00h r/w symbol 76543210 egp 00000 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 76543210 egn 00000 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 2) 0 0 interrupt disable 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges
232 chapter 19 interrupt functions (5) prescaler mode register (prm0) this register specifies the valid edge for ti00/p40 to ti02/p42 pins input. prm0 is set with an 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 19-6. prescaler mode register (prm0) format address: ff70h after reset: 00h r/w symbol 76543210 prm0 es21 es20 es11 es10 es01 es00 prm01 prm00 es21 es20 ti02 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es11 es10 ti01 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es01 es00 ti00 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges caution set the valid edge of the ti00/p40 to ti02/p42 pins after setting bit 2 of 16-bit timer mode control register 0 (tmc0) to 0 to stop the timer operation.
233 chapter 19 interrupt functions (6) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for an interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control multiple processing are mapped. besides 8-bit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, if the brk instruction is executed, the contents of psw are automatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specify flag of the acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with the push psw instruction. they are reset from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 19-7. program status word format 7 ie 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disable) ie 0 1 disable priority of interrupt currently being serviced interrupt request acknowledge enable/disable used when normal instruction is executed enable interrupt request not acknowledged, or low- priority interrupt servicing. (all maskable interrupts enable) 0 1
234 chapter 19 interrupt functions 19.4 interrupt servicing operations 19.4.1 non-maskable interrupt request acknowledge operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. it does not undergo interrupt priority control and has highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag and isp flag are reset (to 0), and the contents of the vector table are loaded into pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction is executed. however, if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one non- maskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program execution. figures 19-8, 19-9, and 19-10 show the flowchart of the non-maskable interrupt request generation through acknowledge, acknowledge timing of non-maskable interrupt request, and acknowledge operation at multiple non- maskable interrupt request generation, respectively.
235 chapter 19 interrupt functions figure 19-8. non-maskable interrupt request generation to acknowledge flowchart start wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdt interrupt servicing? interrupt control register not accessed? interval timer no reset processing no interrupt request generation start of interrupt servicing interrupt request held pending no no no yes yes yes yes yes wdtm: watchdog timer mode register wdt : watchdog timer wdtm3 = 0 (with non-maskable interrupt selected)? figure 19-9. non-maskable interrupt request acknowledge timing instruction instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing wdtif interrupt request generated during this interval is acknowledged at . wdtif: watchdog timer interrupt request flag
236 chapter 19 interrupt functions figure 19-10. non-maskable interrupt request acknowledge operation (a) if a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution main routine nmi request <1> execution of 1 instruction nmi request <2> execution of nmi request <1> nmi request <2> held pending servicing of nmi request <2> that was pended (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request <1> execution of 1 instruction execution of nmi request <1> nmi request <2> held pending nmi request <3> held pending servicing of nmi request <2> that was pended nmi request <3> not acknowledged (although two or more nmi requests have been generated, onl y one request is acknowled g ed.) nmi request <2> nmi request <3>
237 chapter 19 interrupt functions 19.4.2 maskable interrupt request acknowledge operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt is cleared to 0. a vectored interrupt request is acknowledged if in the interrupt enable state (when ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until interrupt servicing is performed are listed in table 19-3 below. for the interrupt request acknowledge timing, see the figures 19-12 and 19-13. table 19-3. times from generation of maskable interrupt request until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specify flag is acknowledged first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is acknowledged when it becomes acknowledgeable. figure 19-11 shows the interrupt request acknowledge algorithm. if a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of program status word (psw), then program counter (pc), the ie flag is reset (to 0), and the contents of the priority specify flag corresponding to the acknowledged interrupt are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into pc and branched. return from an interrupt is possible with the reti instruction.
238 chapter 19 interrupt functions figure 19-11. interrupt request acknowledge processing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any interrupt request among those simultaneously generated? any interrupt request among those simultaneously generated with pr = 0? if : interrupt request flag mk : interrupt mask flag pr : priority specify flag ie : flag that controls acknowledge of maskable interrupt request (1 = enable, 0 = disable) isp : flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledged, or low-priority interrupt servicing)
239 chapter 19 interrupt functions figure 19-12. interrupt request acknowledge timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 19-13. interrupt request acknowledge timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 19.4.3 software interrupt request acknowledge operation a software interrupt acknowledge is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (to 0), and the contents of the vector table (003eh, 003fh) are loaded into pc and branched. return from a software interrupt is possible with the retb instruction. caution do not use the reti instruction for returning from the software interrupt.
240 chapter 19 interrupt functions 19.4.4 multiple interrupt servicing multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt. multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (ie = 1) (except non-maskable interrupts). also, when an interrupt request is received, interrupt requests acknowledge becomes disabled (ie = 0). therefore, to enable multiple interrupts, it is necessary to set (to 1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledge. moreover, even if interrupts are enabled, multiple interrupts may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupts. in the interrupt enable state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held pending. when servicing of the current interrupt ends, the pended interrupt request is acknowledged following execution of one main processing instruction execution. multiple interrupt servicing is not possible during non-maskable interrupt servicing. table 19-4 shows interrupt requests enabled for multiple interrupt servicing, and figure 19-14 shows multiple interrupt examples. table 19-4. interrupt request enabled for multiple interrupt during interrupt servicing multiple interrupt request maskable interrupt request non-maskable interrupt request pr = 0 pr = 1 interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt maskable interrupt isp = 0 isp = 1 software interrupt remarks 1. : multiple interrupt enable 2. : multiple interrupt disable 3. isp and ie are flags contained in psw. isp = 0 : an interrupt with higher priority is being serviced. isp = 1 : no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0 : interrupt request acknowledge is disabled. ie = 1 : interrupt request acknowledge is enabled. 4. pr is a flag contained in pr0l, pr0h, and pr1l. pr = 0 : higher priority level pr = 1 : lower priority level
241 chapter 19 interrupt functions figure 19-14. multiple interrupt examples (1/2) example 1. multiple interrupts occur twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 during servicing of interrupt intxx, two interrupt requests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledge. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0 : higher priority level pr = 1 : lower priority level ie = 0 : interrupt request acknowledge disable
242 chapter 19 interrupt functions figure 19-14. multiple interrupt examples (2/2) example 3. multiple interrupt servicing does not occur because interrupt is not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 interrupt is not enabled during servicing of interrupt intxx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0 : higher priority level ie = 0 : interrupt request acknowledge disable
243 chapter 19 interrupt functions 19.4.5 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. these instructions (interrupt request hold instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw.bit, cy ? mov1 cy, psw.bit ? and1 cy, psw.bit ? or1 cy, psw.bit ? xor1 cy, psw.bit ? set1 psw.bit ? clr1 psw.bit ? retb ? reti ? push psw ? pop psw ? bt psw.bit, $addr16 ? bf psw.bit, $addr16 ? btclr psw.bit, $addr16 ?ei ?di ? manipulate instructions for the if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, egp, and egn registers caution the brk instruction is not one of the above-listed interrupt request hold instruction. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. however, a non-maskable interrupt request is acknowledged. the timing with which interrupt requests are held pending is shown in figure 19-15. figure 19-15. interrupt request hold instruction n instruction m save psw and pc, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other than interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request).
244 [memo]
245 chapter 20 standby function 20.1 standby function and configuration 20.1.1 standby function the standby function is designed to decrease power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. the system clock oscillator continues oscillating. in this mode, current consumption is not decreased as much as in the stop mode. however, the halt mode is effective to restart operation immediately upon interrupt request and to carry out intermittent operations such as watch operation. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops, stopping the whole system, thereby considerably reducing the cpu current consumption. data memory low-voltage hold (down to v dd = 2.0 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is required to secure an oscillation stabilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. in either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. the input/output port output latch and output buffer status are also held. cautions 1. when operation is transferred to the stop mode, be sure to stop the peripheral hardware operation and execute the stop instruction. 2. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs1) of the a/d converter mode register (adm1) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction.
246 chapter 20 standby function 20.1.2 standby function control register the wait time after the stop mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. figure 20-1. oscillation stabilization time select register (osts) format address: fffah after reset: 04h r/w symbol 76543210 osts 00000 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time 0002 12 /f x (488 m s) 0012 14 /f x (1.95 ms) 0102 15 /f x (3.91 ms) 0112 16 /f x (7.81 ms) 1002 17 /f x (15.6 ms) other than above setting prohibited caution the wait time after the stop mode is cleared does not include the time (see a in the illustration below) from stop mode clear to clock oscillation start, regardless of clearance by reset input or by interrupt request generation. stop mode clear x1 pin voltage waveform v ss a remarks 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation with f x = 8.38 mhz.
247 chapter 20 standby function 20.2 standby function operations 20.2.1 halt mode (1) halt mode setting and operating status the halt mode is set by executing the halt instruction. the operating status in the halt mode is described below. table 20-1. halt mode operating status halt mode setting during halt instruction execution using main system clock item clock generator main system clock can be oscillated. clock supply to cpu stops. cpu operation stops. port (output latch) status before halt mode setting is held. 16-bit timer operable 8-bit timer watch timer watchdog timer a/d converter operation stops. serial interface operable lcd controller/driver external interrupt sound generator meter controller/driver
248 chapter 20 standby function (2) halt mode clear the halt mode can be cleared with the following three types of sources. (a) clear upon unmasked interrupt request an unmasked interrupt request is used to clear the halt mode. if interrupt acknowledge is enabled, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 20-2. halt mode clear upon interrupt generation halt instruction wait wait operating mode halt mode operating mode oscillation clock standby release signal remarks 1. the broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged. 2. wait times are as follows: ? when vectored interrupt service is carried out : 8 to 9 clocks ? when vectored interrupt service is not carried out : 2 to 3 clocks (b) clear upon non-maskable interrupt request the halt mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled.
249 chapter 20 standby function (c) clear upon reset input as in the case with normal reset operation, a program is executed after branch to the reset vector address. figure 20-3. halt mode clear upon reset input halt instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode halt mode operating mode oscillation stop clock reset signal oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation with f x = 8.38 mhz. table 20-2. operation after halt mode clear clear source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0101 next address instruction execution 01 0 0111 interrupt service execution 1 halt mode hold non-maskable interrupt request interrupt service execution reset input reset processing : dont care
250 chapter 20 standby function 20.2.2 stop mode (1) stop mode setting and operating status the stop mode is set by executing the stop instruction. cautions 1. when the stop mode is set, the x2 pin is internally connected to v dd via a pull-up resistor to minimize the leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait set using the oscillation stabilization time select register (osts), the operating mode is set. the operating status in the stop mode is described below. table 20-3. stop mode operating status stop mode setting during stop instruction execution using main system clock item clock generator only main system clock oscillation is stopped. cpu operation stops. port (output latch) status before stop mode setting is held. 16-bit timer operation stops. 8-bit timer operable only when tio2 and tio3 are selected as count clock. watch timer operation stops. watchdog timer operation stops. a/d converter operation stops. serial interface other than uart operable only when externally supplied input clock is specified as the serial clock. uart operation stops. lcd controller/driver operation stops. external interrupt operable sound generator operation stops. meter controller/driver operation stops.
251 chapter 20 standby function (2) stop mode clear the stop mode can be cleared with the following two types of sources. (a) clear upon unmasked interrupt request an unmasked interrupt request is used to clear the stop mode. if interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 20-4. stop mode clear upon interrupt generation stop instruction wait (time set by osts) oscillation stabilization wait status operating mode stop mode operating mode oscillation clock standby release signal oscillation stop oscillation remark the broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged.
252 chapter 20 standby function (b) clear upon reset input the stop mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. figure 20-5. stop mode clear upon reset input stop instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode stop mode operating mode oscillation stop clock reset signal oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation with f x = 8.38 mhz. table 20-4. operation after stop mode clear clear source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0101 next address instruction execution 01 0 0111 interrupt service execution 1 stop mode hold reset input reset processing : dont care
253 chapter 21 reset function 21.1 reset function the following two operations are available to generate the reset signal. (1) external reset input with reset pin (2) internal reset by watchdog timer overrun time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in table 21-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset pin, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ). the reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ) (see figures 21-2 to 21- 4). cautions 1. for an external reset, input a low level for 10 m s or more to the reset pin. 2. during reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pin becomes high-impedance. figure 21-1. reset function block diagram reset count clock reset control circuit watchdog timer stop overflow reset signal interrupt function
254 chapter 21 reset function figure 21-2. timing of reset by reset input delay delay hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin figure 21-3. timing of reset due to watchdog timer overflow hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 watchdog timer overflow internal reset signal port pin figure 21-4. timing of reset in stop mode by reset input delay delay hi-z normal operation oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin stop status (oscillation stop) stop instruction execution reset period (oscillation stop)
255 chapter 21 reset function table 21-1. hardware status after reset (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general register undefined note 2 port (output latch) 00h port mode registers (pm0 to pm6, pm8, pm9) ffh pull-up resistor option register (pu0) 00h processor clock control register (pcc) 04h memory size switching register (ims) cfh oscillation stabilization time select register (osts) 04h oscillator mode register (oscm) note 3 00h 16-bit timer tm0 timer register (tm0) 00h capture registers (cr00 to cr02) 00h prescaler mode register (prm0) 00h mode control register (tmc0) 00h capture pulse control register (crc0) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware status become undefined. all other hardware statuses remain unchanged after reset. 2. the post-reset status is held in the standby mode. 3. for m pd780973(a) only.
256 chapter 21 reset function table 21-1. hardware status after reset (2/2) hardware status after reset 8-bit timer tm1 to tm3 timer counters (tm1 to tm3) 00h compare registers (cr1 to cr3) 00h clock select registers (tcl1 to tcl3) 00h mode control registers (tmc1 to tmc3) 04h watch timer mode control register (wtm) 00h watchdog timer clock select register (wdcs) 00h mode register (wdtm) 00h a/d converter conversion result register (adcr1) 00h mode register (adm1) 00h analog input channel specification register (ads1) 00h power-fail compare mode register (pfm) 00h power-fail compare threshold value register (pft) 00h serial interface uart asynchronous serial interface mode register (asim) 00h asynchronous serial interface status register (asis) 00h baud rate generator control register (brgc) 00h transmit shift register (txs) ffh receive buffer register (rxb) serial interface sio3 shift register (sio) 00h mode register (csim) 00h lcd controller/driver display mode register (lcdm) 00h display control register (lcdc) 00h eeprom write control register (eewc) 00h sound generator control register (sgcr) 00h buzzer control register (sgbr) 00h amplitude register (sgam) 00h meter controller/driver compare registers (mcmp10, mcmp11, mcmp20, 00h mcmp21, mcmp30, mcmp31, mcmp40, mcmp41) timer mode control register (mcntc) 00h port mode control register (pmc) 00h compare control registers (mcmpc1 to mcmpc3) 00h interrupt request flag registers (if0l, if0h, if1l) 00h mask flag registers (mk0l, mk0h, mk1l) ffh priority specify flag registers (pr0l, pr0h, pr1l) ffh external interrupt rising edge enable register (egp) 00h external interrupt falling edge enable register (egn) 00h
257 chapter 22 m pd78f0974 the m pd78f0974 replace the internal rom of the m pd780973(a) with flash memory to which a program can be written, deleted and overwritten while mounted on a board. table 22-1 lists the differences between the m pd78f0974 and the m pd780973(a). table 22-1. differences between m pd78f0974 and m pd780973(a) item m pd78f0974 m pd780973(a) rom type flash memory mask rom internal rom capacity 32 kbytes 24 kbytes internal high-speed ram capacity 1024 bytes 768 bytes change of internal rom and internal possible note not provided high-speed ram capacity using memory size switching register ic pin none available v pp pin available none electrical specifications see data sheet of each product. quality grade standard special note although the initial value is cfh, set the following values. ims setting value flash memory internal remarks high-speed ram 06h 24 kbytes 768 bytes when using the same memory map as that of m pd780973(a) c8h 32 kbytes 1024 bytes when using the maximum value caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version.
258 chapter 22 m pd78f0974 22.1 memory size switching register the m pd78f0974 allow users to select the internal memory capacity using the memory size switching register (ims) so that the same memory map as that of the m pd780973(a) with a different size of internal memory capacity can be achieved. ims is set by using an 8-bit memory manipulation instruction. reset input sets ims to cfh. figure 22-1. memory size switching register (ims) format address: fff0h after reset: cfh r/w symbol 76543210 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal high-speed ram capacity selection 0 0 0 768 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 011024 kbytes 100032 kbytes other than above setting prohibited the ims settings to obtain the same memory map as the m pd780973(a) are shown in table 22-2. table 22-2. memory size switching register settings product ims setting m pd780973(a) 06h caution with the m pd780973(a), ims must be set to 06h.
259 chapter 22 m pd78f0974 22.2 flash memory programming on-board writing of flash memory (with device mounted on target system) is supported. on-board writing is done after connecting a dedicated flash writer (flashpro ii) to the host machine and target system. moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to flashpro ii. remark flashpro ii is a product of naitou densei machidaseisakusho co., ltd. 22.2.1 selection of transmission method writing to flash memory is performed using flashpro ii and serial communication. select the transmission method for writing from table 22-3. for the selection of the transmission method, a format like the one shown in figure 22-2 is used. the transmission methods are selected with the v pp pulse numbers shown in table 22-3. table 22-3. transmission method list transmission method number of channels pin used number of v pp pulses 3-wire serial i/o 1 si/p52 0 so/p51 sck/p50 uart 1 rxd/p53 8 txd/p54 pseudo 3-wire serial i/o 2 p05 (serial clock input) 12 p06 (serial data output) p07 (serial data input) p95/s7 (serial clock input) 13 p96/s6 (serial data output) p97/s5 (serial data input) cautions 1. be sure to select the number of v pp pulses shown in table 22-3 for the transmission method. 2. if performing write operations to flash memory with the uart transmission method, set the main system clock oscillation frequency to 4.19 mhz or higher. figure 22-2. transmission method selection format 10 v v pp reset v dd v ss v dd v ss v pp pulses flash write mode
260 chapter 22 m pd78f0974 22.2.2 flash memory programming function flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. the main functions are listed in table 22-4. table 22-4. main functions of flash memory programming function description reset detects write stop and transmission synchronization. batch verify compares entire memory contents and input data. batch delete deletes the entire memory contents. batch blank check checks the deletion status of the entire memory. high-speed write performs writing to flash memory according to write start address and number of write data (bytes). continuous write performs successive write operations using the data input with high-speed write operation. status checks the current operation mode and operation end. oscillation frequency setting inputs the resonator oscillation frequency information. delete time setting inputs the memory delete time. baud rate setting sets the transmission rate when the uart method is used. silicon signature read outputs the device name, memory capacity, and device block information. 22.2.3 flashpro ii connection connection of flashpro ii and the m pd78f0974 differs depending on transmission method (3-wire serial i/o, uart, and pseudo 3-wire serial i/o). each case of connection shows in figures 22-3, 22-4, and 22-5. figure 22-3. flashpro ii connection using 3-wire serial i/o method v pp v dd reset sck so si gnd v pp v dd reset sck si so v ss flashpro ii pd78f0974 m
261 chapter 22 m pd78f0974 figure 22-4. flashpro ii connection using uart method figure 22-5. flashpro ii connection using pseudo 3-wire serial i/o method v pp v dd reset sck so si gnd v pp v dd reset p05, p95 (serial clock input) p07, p97 (serial data input) p06, p96 (serial data output) v ss flashpro ii pd78f0974 m v pp v dd reset so si gnd v pp v dd reset rxd txd v ss flashpro ii pd78f0974 m
262 [memo]
263 chapter 23 instruction set this chapter lists the instruction set of the m pd780973 subseries. for details of the operation and machine language (instruction code), refer to the separate document 78k/0 series users manualinstructions (u12326e) .
264 chapter 23 instruction set 23.1 legend for operation list 23.1.1 operand identifiers and description formats operands are described in operand column of each instruction in accordance with the description format of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description formats, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. the meaning of the symbols are as follows. ? # : immediate data ? ! : absolute address ? $ : relative address ? [ ] : indirect address in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 23-1. operand identifiers and description formats identifier description format r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even addresses only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special-function register symbols, refer to table 3-5 special function register list .
265 chapter 23 instruction set 23.1.2 description of operation column a : a register; 8-bit accumulator x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag rbs : register bank select flag ie : interrupt request enable flag nmis : non-maskable interrupt servicing flag ( ) : memory contents indicated by address or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 23.1.3 description of flag operation column (blank) : not affected 0 : cleared to 0 1 : set to 1 : set/cleared according to the result r : previously saved value is restored
266 chapter 23 instruction set 23.2 operation list clock flag note 1 note 2 zaccy r, #byte 2 4 C r ? byte saddr, #byte 3 6 7 (saddr) ? byte sfr, #byte 3 C 7 sfr ? byte a, r note 3 12 Ca ? r r, a note 3 12 Cr ? a a, saddr 2 4 5 a ? (saddr) saddr, a 2 4 5 (saddr) ? a a, sfr 2 C 5 a ? sfr sfr, a 2 C 5 sfr ? a a, !addr16 3 8 9 a ? (addr16) !addr16, a 3 8 9 (addr16) ? a psw, #byte 3 C 7 psw ? byte a, psw 2 C 5 a ? psw psw, a 2 C 5 psw ? a a, [de] 1 4 5 a ? (de) [de], a 1 4 5 (de) ? a a, [hl] 1 4 5 a ? (hl) [hl], a 1 4 5 (hl) ? a a, [hl + byte] 2 8 9 a ? (hl + byte) [hl + byte], a 2 8 9 (hl + byte) ? a a, [hl + b] 1 6 7 a ? (hl + b) [hl + b], a 1 6 7 (hl + b) ? a a, [hl + c] 1 6 7 a ? (hl + c) [hl + c], a 1 6 7 (hl + c) ? a a, r note 3 12 Ca ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 C 6 a ? sfr a, !addr16 3 8 10 a ? (addr16) xch a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except r = a remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). mnemonic operands byte operation instruction group 8-bit data transfer mov
267 chapter 23 instruction set clock flag note 1 note 2 zaccy rp, #word 3 6 C rp ? word saddrp, #word 4 8 10 (saddrp) ? word sfrp, #word 4 C 10 sfrp ? word ax, saddrp 2 6 8 ax ? (saddrp) saddrp, ax 2 6 8 (saddrp) ? ax movw ax, sfrp 2 C 8 ax ? sfrp sfrp, ax 2 C 8 sfrp ? ax ax, rp note 3 1 4 C ax ? rp rp, ax note 3 1 4 C rp ? ax ax, !addr16 3 10 12 ax ? (addr16) !addr16, ax 3 10 12 (addr16) ? ax xchw ax, rp note 3 1 4 C ax ? rp a, #byte 2 4 C a, cy ? a + byte saddr, #byte 3 6 8 (saddr), cy ? (saddr) + byte a, r note 4 2 4 C a, cy ? a + r r, a 2 4 C r, cy ? r + a a, saddr 2 4 5 a, cy ? a + (saddr) a, !addr16 3 8 9 a, cy ? a + (addr16) a, [hl] 1 4 5 a, cy ? a + (hl) a, [hl + byte] 2 8 9 a, cy ? a + (hl + byte) a, [hl + b] 2 8 9 a, cy ? a + (hl + b) a, [hl + c] 2 8 9 a, cy ? a + (hl + c) a, #byte 2 4 C a, cy ? a + byte + cy saddr, #byte 3 6 8 (saddr), cy ? (saddr) + byte + cy a, r note 4 2 4 C a, cy ? a + r + cy r, a 2 4 C r, cy ? r + a + cy a, saddr 2 4 5 a, cy ? a + (saddr) + cy a, !addr16 3 8 9 a, cy ? a + (addr16) + cy a, [hl] 1 4 5 a, cy ? a + (hl) + cy a, [hl + byte] 2 8 9 a, cy ? a + (hl + byte) + cy a, [hl + b] 2 8 9 a, cy ? a + (hl + b) + cy a, [hl + c] 2 8 9 a, cy ? a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except r = a remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). mnemonic operands byte operation instruction group 16-bit data transfer add addc 8-bit operation
268 chapter 23 instruction set clock flag note 1 note 2 zaccy a, #byte 2 4 C a, cy ? a C byte saddr, #byte 3 6 8 (saddr), cy ? (saddr) C byte a, r note 3 2 4 C a, cy ? a C r r, a 2 4 C r, cy ? r C a a, saddr 2 4 5 a, cy ? a C (saddr) a, !addr16 3 8 9 a, cy ? a C (addr16) a, [hl] 1 4 5 a, cy ? a C (hl) a, [hl + byte] 2 8 9 a, cy ? a C (hl + byte) a, [hl + b] 2 8 9 a, cy ? a C (hl + b) a, [hl + c] 2 8 9 a, cy ? a C (hl + c) a, #byte 2 4 C a, cy ? a C byte C cy saddr, #byte 3 6 8 (saddr), cy ? (saddr) C byte C cy a, r note 3 2 4 C a, cy ? a C r C cy r, a 2 4 C r, cy ? r C a C cy a, saddr 2 4 5 a, cy ? a C (saddr) C cy a, !addr16 3 8 9 a, cy ? a C (addr16) C cy a, [hl] 1 4 5 a, cy ? a C (hl) C cy a, [hl + byte] 2 8 9 a, cy ? a C (hl + byte) C cy a, [hl + b] 2 8 9 a, cy ? a C (hl + b) C cy a, [hl + c] 2 8 9 a, cy ? a C (hl + c) C cy a, #byte 2 4 C a ? a byte saddr, #byte 3 6 8 (saddr) ? (saddr) byte a, r note 3 24 Ca ? a r r, a 2 4 C r ? r a a, saddr 2 4 5 a ? a (saddr) a, !addr16 3 8 9 a ? a (addr16) a, [hl] 1 4 5 a ? a (hl) a, [hl + byte] 2 8 9 a ? a (hl + byte) a, [hl + b] 2 8 9 a ? a (hl + b) a, [hl + c] 2 8 9 a ? a (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). mnemonic operands byte operation instruction group sub subc and 8-bit operation
269 chapter 23 instruction set clock flag note 1 note 2 zaccy a, #byte 2 4 C a ? a byte saddr, #byte 3 6 8 (saddr) ? (saddr) byte a, r note 3 24 Ca ? a r r, a 2 4 C r ? r a a, saddr 2 4 5 a ? a (saddr) a, !addr16 3 8 9 a ? a (addr16) a, [hl] 1 4 5 a ? a (hl) a, [hl + byte] 2 8 9 a ? a (hl + byte) a, [hl + b] 2 8 9 a ? a (hl + b) a, [hl + c] 2 8 9 a ? a (hl + c) a, #byte 2 4 C a ? a byte saddr, #byte 3 6 8 (saddr) ? (saddr) byte a, r note 3 24 Ca ? a r r, a 2 4 C r ? r a a, saddr 2 4 5 a ? a (saddr) a, !addr16 3 8 9 a ? a (addr16) a, [hl] 1 4 5 a ? a (hl) a, [hl + byte] 2 8 9 a ? a (hl + byte) a, [hl + b] 2 8 9 a ? a (hl + b) a, [hl + c] 2 8 9 a ? a (hl + c) a, #byte 2 4 C a C byte saddr, #byte 3 6 8 (saddr) C byte a, r note 3 24 Ca C r r, a 2 4 C r C a a, saddr 2 4 5 a C (saddr) a, !addr16 3 8 9 a C (addr16) a, [hl] 1 4 5 a C (hl) a, [hl + byte] 2 8 9 a C (hl + byte) a, [hl + b] 2 8 9 a C (hl + b) a, [hl + c] 2 8 9 a C (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). mnemonic operands byte operation instruction group or xor cmp 8-bit operation
270 chapter 23 instruction set clock flag note 1 note 2 zaccy addw ax, #word 3 6 C ax, cy ? ax + word subw ax, #word 3 6 C ax, cy ? ax C word cmpw ax, #word 3 6 C ax C word mulu x 2 16 C ax ? a x divuw c 2 25 C ax (quotient), c (remainder) ? ax ? c r12Cr ? r + 1 saddr 2 4 6 (saddr) ? (saddr) + 1 r12Cr ? r C 1 saddr 2 4 6 (saddr) ? (saddr) C 1 incw rp 1 4 C rp ? rp + 1 decw rp 1 4 C rp ? rp C 1 ror a, 1 1 2 C (cy, a 7 ? a 0 , a m C 1 ? a m ) 1 time rol a, 1 1 2 C (cy, a 0 ? a 7 , a m + 1 ? a m ) 1 time rorc a, 1 1 2 C (cy ? a 0 , a 7 ? cy, a m C 1 ? a m ) 1 time rolc a, 1 1 2 C (cy ? a 7 , a 0 ? cy, a m + 1 ? a m ) 1 time a 3 C 0 ? (hl) 3 C 0 , (hl) 7 C 4 ? a 3 C 0 , (hl) 3 C 0 ? (hl) 7 C 4 a 3 C 0 ? (hl) 7 C 4 , (hl) 3 C 0 ? a 3 C 0 , (hl) 7 C 4 ? (hl) 3 C 0 decimal adjust accumulator after addition decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy ? (saddr.bit) cy, sfr.bit 3 C 7 cy ? sfr.bit cy, a.bit 2 4 C cy ? a.bit cy, psw.bit 3 C 7 cy ? psw.bit cy, [hl].bit 2 6 7 cy ? (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) ? cy sfr.bit, cy 3 C 8 sfr.bit ? cy a.bit, cy 2 4 C a.bit ? cy psw.bit, cy 3 C 8 psw.bit ? cy [hl].bit, cy 2 6 8 (hl).bit ? cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). mnemonic operands byte operation instruction group inc 16-bit operation increment/ decrement dec rotate ror4 [hl] 2 10 12 rol4 [hl] 2 10 12 adjba 24 C adjbs 24 C bcd adjust mov1 bit manipu- late multiply/ divide
271 chapter 23 instruction set clock flag note 1 note 2 zaccy cy, saddr.bit 3 6 7 cy ? cy (saddr.bit) cy, sfr.bit 3 C 7 cy ? cy sfr.bit and1 cy, a.bit 2 4 C cy ? cy a.bit cy, psw.bit 3 C 7 cy ? cy psw.bit cy, [hl].bit 2 6 7 cy ? cy (hl).bit cy, saddr.bit 3 6 7 cy ? cy (saddr.bit) cy, sfr.bit 3 C 7 cy ? cy sfr.bit or1 cy, a.bit 2 4 C cy ? cy a.bit cy, psw.bit 3 C 7 cy ? cy psw.bit cy, [hl].bit 2 6 7 cy ? cy (hl).bit cy, saddr.bit 3 6 7 cy ? cy (saddr.bit) cy, sfr.bit 3 C 7 cy ? cy sfr.bit xor1 cy, a.bit 2 4 C cy ? cy a.bit cy, psw.bit 3 C 7 cy ? cy psw.bit cy, [hl].bit 2 6 7 cy ? cy (hl).bit saddr.bit 2 4 6 (saddr.bit) ? 1 sfr.bit 3 C 8 sfr.bit ? 1 set1 a.bit 2 4 C a.bit ? 1 psw.bit 2 C 6 psw.bit ? 1 [hl].bit 2 6 8 (hl).bit ? 1 saddr.bit 2 4 6 (saddr.bit) ? 0 sfr.bit 3 C 8 sfr.bit ? 0 clr1 a.bit 2 4 C a.bit ? 0 psw.bit 2 C 6 psw.bit ? 0 [hl].bit 2 6 8 (hl).bit ? 0 set1 cy 1 2 C cy ? 11 clr1 cy 1 2 C cy ? 00 not1 cy 1 2 C cy ? cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). mnemonic operands byte operation instruction group bit manipu- late
272 chapter 23 instruction set mnemonic operands byte operation instruction group call !addr16 3 7 C callt [addr5] 1 6 C retb 16 C rrr ret 16 C rp 1 4 C rp 1 4 C push pop uncondi- tional branch stack manipu- late conditional branch call/return clock flag note 1 note 2 zaccy (sp C 1) ? (pc + 3) h , (sp C 2) ? (pc + 3) l , pc ? addr16, sp ? sp C 2 (sp C 1) ? (pc + 2) h , (sp C 2) ? (pc + 2) l , callf !addr11 2 5 C pc 15 C 11 ? 00001, pc 10 C 0 ? addr11, sp ? sp C 2 (sp C 1) ? (pc + 1) h , (sp C 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp C 2 (sp C 1) ? psw, (sp C 2) ? (pc + 1) h , brk 1 6 C (sp C 3) ? (pc + 1) l , pc h ? (003fh), pc l ? (003eh), sp ? sp C 3, ie ? 0 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 pc h ? (sp + 1), pc l ? (sp), reti 1 6 C psw ? (sp + 2), sp ? sp + 3, r r r nmis ? 0 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3 psw 1 2 C (sp C 1) ? psw, sp ? sp C 1 (sp C 1) ? rp h , (sp C 2) ? rp l , sp ? sp C 2 psw 1 2 C psw ? (sp), sp ? sp + 1 r r r rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 sp, #word 4 C 10 sp ? word movw sp, ax 2 C 8 sp ? ax ax, sp 2 C 8 ax ? sp !addr16 3 6 C pc ? addr16 br $addr16 2 6 C pc ? pc + 2 + jdisp8 ax 2 8 C pc h ? a, pc l ? x bc $addr16 2 6 C pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 C pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 C pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 C pc ? pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc).
273 chapter 23 instruction set clock flag note 1 note 2 zaccy saddr.bit, $addr16 3 8 9 pc ? pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 C 11 pc ? pc + 4 + jdisp8 if sfr.bit = 1 bt a.bit, $addr16 3 8 C pc ? pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 C 9 pc ? pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 pc ? pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc ? pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 C 11 pc ? pc + 4 + jdisp8 if sfr.bit = 0 bf a.bit, $addr16 3 8 C pc ? pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 C 11 pc ? pc + 4 + jdisp8 if psw.bit = 0 [hl].bit, $addr16 3 10 11 pc ? pc + 3 + jdisp8 if (hl).bit = 0 saddr.bit, $addr16 4 10 12 pc ? pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) pc ? pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit btclr pc ? pc + 3 + jdisp8 if a.bit = 1 then reset a.bit pc ? pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit pc ? pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b ? b C 1, then pc ? pc + 2 + jdisp8 if b 1 0 c ? c C 1, then pc ? pc + 2 + jdisp8 if c 1 0 (saddr) ? (saddr) C 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 sel rbn 2 4 C rbs1, 0 ? n nop 1 2 C no operation ei 2 C 6 ie ? 1 (enable interrupt) di 2 C 6 ie ? 0 (disable interrupt) halt 2 6 C set halt mode stop 2 6 C set stop mode notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). sfr.bit, $addr16 4 C 12 a.bit, $addr16 3 8 C psw.bit, $addr16 4 C 12 [hl].bit, $addr16 3 10 12 b, $addr16 2 6 C dbnz c, $addr16 2 6 C saddr, $addr16 3 8 10 mnemonic operands byte operation instruction group cpu control condi- tional branch
274 chapter 23 instruction set 23.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz
275 chapter 23 instruction set second operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none first operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a
276 chapter 23 instruction set (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 #word ax rp note sfrp saddrp !addr16 sp none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none
277 chapter 23 instruction set ax !addr16 !addr11 [addr5] $addr16 (4) call/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
278 [memo]
279 appendix a development tools the following development tools are available for the development of systems that employ the m pd780973 subseries. figure a-1 shows the development tool configuration.
280 appendix a development tools figure a-1. development tool configuration (1/2) (1) when using in-circuit emulator ie-78k0-ns ?system simulator ?integrated debugger ?device file embedded software ?real-time os ?os debugging tools ?assembler package ?c compiler package ?c library source file ?device file language processing software on-chip flash memory version in-circuit emulator power unit emulation probe conversion socket or conversion adapter target system host machine (pc) interface adapter, pc card interface, etc. emulation board flash programmer flash memory writing environment
281 appendix a development tools figure a-1. development tool configuration (2/2) (2) when using in-circuit emulator ie-78001-r-a remark the tool enclosed in a broken line depends on the development environment. refer to a.3.1 hard- ware . ? system simulator ? integrated debugger ? device file embedded software ? real-time os ? os debugging tools ? assembler package ? c compiler package ? c library source file ? device file language processing software in-circuit emulator emulation probe conversion socket or conversion adapter target system host machine (pc or ews) interface board interface adapter cpu core board i/o board probe board on-chip flash memory version flash memory writing environment flash programmer
282 appendix a development tools a.1 language processing software notes 1. the df780974 is used in common with the ra78k/0, cc78k/0, sm78k0, id78k0-ns, and id78k0. 2. under development remark in the part number differs depending on the host machine and os used. ra78k/0 this assembler converts programs written in mnemonics into an object code assembler package executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler is used in combination with an optional device file (df780974). this assembler package is a dos-based application, however using project manager, which is included in the assembler package, enables use of this assembler in a windows environment. part number: m s ra78k0 cc78k/0 this compiler converts programs written in c language into an object code executable c compiler package with a microcontroller. this compiler is used in combination with an optional assembler package (ra78k/0) and device file (df780974). this c compiler package is a dos-based application, however using project manager, which is included in the assembler package, enables use of this compiler in a windows environment. part number: m s cc78k0 df780974 notes 1, 2 this file contains information peculiar to the device. device file this file is used in combination with each optional tools ra78k/0, cc78k/0, sm78k0, id78k0-ns, and id78k0. supported os and host machine depend on each tool. part number: m s df780974 cc78k/0-l this is a source of functions configuring the object library included in the c compiler c library source file package. it is required for matching the object library included in the c compiler package with to the customers specifications. operation environment does not depend on os because the source file is used. part number: m s cc78k0-l
283 appendix a development tools m s ra78k0 m s cc78k0 m s df780974 m s cc78k0-l host machine os supply medium aa13 pc-9800 series windows 3.5-inch 2hd fd japanese version notes 1, 2 ab13 ibm pc/at? and compatibles windows 3.5-inch 2hc fd japanese version notes 1, 2 bb13 windows english version notes 1, 2 3p16 hp9000 series 700? hp-ux? (rel. 9.05) dat (dds) 3k13 sparcstation? sunos? (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news? (risc) news-os? (rel. 6.1) 3.5-inch 2hc fd notes 1. dos is also supported. 2. windowsnt? is not supported. a.2 flash memory writing tools flashpro ii (fl-pr2) flash writer remark flashpro ii is a product of naitou densei machidaseisakusho co., ltd. naitou densei machidaseisakusho co., ltd. (tel +81-44-822-3813) dedicated flash writer for microcontrollers with on-chip flash memory.
284 appendix a development tools a.3 debugging tools a.3.1 hardware (1/2) (1) when using in-circuit emulator ie-78k0-ns ie-78k0-ns note this in-circuit emulator is used to debug hardware and software when developing application in-circuit emulator systems using the 78k/0 series. it supports the integrated debugger (id78k0-ns). this emulator is used in combination with a power unit, an emulation probe, and an interface adapter for connection to a host machine. ie-70000-mc-ps-b this is an adapter for power supply from a receptacle of 100-v to 240-v ac. power unit ie-70000-98-if-c note this adapter is required when using the pc-9800 series computer (except notebook type) as interface adapter the ie-78k0-ns host machine. ie-70000-cd-if note these pc card and interface cable are required when using a pc-9800 series notebook as the pc card interface ie-78k0-ns host machine. ie-70000-pc-if-c note this adapter is required when using an ibm pc/at or compatible as the ie-78k0-ns host interface adapter machine. ie-780974-ns-em1 note this board is used to emulate the peripheral hardware that is peculiar to the device. this emulation board board is used in combination with an in-circuit emulator. ep-80gf-ns this probe is used to connect an in-circuit emulator and target system. it is for 80-pin plastic emulation probe qfps (gf-3b9 type). tgf-080rap this conversion adapter is used to connect a target system board designed to allow conversion adapter mounting of an 80-pin plastic qfp (gf-3b9 type) and the ep80gf-ns. (refer to figure a-2) note under development remarks 1. tgf-080rap is a product of tokyo eletech corporation. for inquiry: daimaru kougyou corporation phone: +81-3-3820-7112 tokyo electronic components division +81-6-244-6672 osaka electronic components division 2. the tgf-080rap is sold in single units.
285 appendix a development tools a.3.1 hardware (2/2) (2) when using in-circuit emulator ie-78001-r-a ie-78001-r-a note in-circuit emulator ie-70000-98-if-b or ie-70000-98-if-c note interface adapter ie-70000-pc-if-b or ie-70000-pc-if-c note interface adapter ie-78000-r-sv3 interface adapter ie-78k0-sl-em note cpu core board ie-780974-sl-em1 probe board ep-80gf-sl emulation probe tgf-080rap conversion adapter (see figure a-2) note under development remarks 1. tgf-080rap is a product of tokyo eletech corporation. for inquiry: daimaru kougyou corporation phone: +81-3-3820-7112 tokyo electronic components division +81-6-244-6672 osaka electronic components division 2. the tgf-080rap is sold in single units. this in-circuit emulator is used to debug hardware and software when developing application systems using the 78k/0 series. it supports the integrated debugger (id78k0). this emulator is used in combination with an emulation probe and an interface adapter for connection to a host machine. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-78001-r-a host machine. this adapter is required when using an ibm pc/at or compatible as the ie-78001-r-a host machine. this is an adapter and cable when an ews is used as the host machine for the ie- 78001-r-a and is connected to the board in the ie-78001-r-a. 10base-5 is supported as ethernet tm . for the other methods, a commercially available conversion adapter is necessary. this board is used to emulate a 78k/0 series cpu. this board is used in combination with an in-circuit emulator and probe board. this board is used to perform mask option settings and pin connection changes. this probe is used to connect an in-circuit emulator and target system. it is for 80-pin plastic qfps (gf-3b9 type). an 80-pin conversion socket (tgf-080rap) is included to facilitate target system development. this conversion adapter is used to connect a target system board designed to allow mounting of an 80-pin plastic qfp (gf-3b9 type) and the ep-80gf-sl.
286 appendix a development tools a.3.2 software (1/2) sm78k0 this system simulator is used to perform debugging at c source level or assembler system simulator level while simulating the operation of the target system on a host machine. the sm78k0 operates on windows. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. the sm78k0 is used in combination with the optional device file (df780974). part number: m s sm78k0 remark in the part number differs depending on the host machine and os used. m s sm78k0 host machine os supply medium aa13 pc-9800 series windows japanese version note 3.5-inch 2hd fd ab13 ibm pc/at and compatibles windows japanese version note 3.5-inch 2hc fd bb13 windows english version note note windowsnt is not supported.
287 appendix a development tools a.3.2 software (2/2) id78k0-ns note integrated debugger (supports in-circuit emulator ie-78k0-ns) id78k0 integrated debugger (supports in-circuit emulator ie-78001-r-a) note under development remark in the part number differs depending on the host machine and os used. m s id78k0-ns host machine os supply medium aa13 pc-9800 series windows japanese version note 3.5-inch 2hd fd ab13 ibm pc/at and compatibles windows japanese version note 3.5-inch 2hc fd bb13 windows english version note note windowsnt is not supported. m s id78k0 host machine os supply medium aa13 pc-9800 series windows japanese version note 3.5-inch 2hd fd ab13 ibm pc/at and compatibles windows japanese version note 3.5-inch 2hc fd bb13 windows english version note 3p16 hp9000 series 700 hp-ux (rel. 9.05) dat (dds) 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news (risc) news-os (rel. 6.1) 3.5-inch 2hc fd note windowsnt is not supported. this is a control program used to debug the 78k/0 series. the graphical user interfaces employed are windows for personal computers and osf/ motif tm for ewss, offering the standard appearance and operability typical of these interfaces. further, debugging functions supporting c language are reinforced, and the trace result can be displayed in c language level by using a window integrating function that associates the source program, disassemble display, and memory display with the trace result. in addition, it can enhance the debugging efficiency of a program using a real-time os by incorporating function expansion modules such as a task debugger and system performance analyzer. this debugger is used in combination with an optional device file (df780974). part number: m s id78k0-ns, m s id78k0
288 appendix a development tools a.4 upgrading former in-circuit emulator for 78k/0 series to ie-78001-r-a if you have a former in-circuit emulator for the 78k/0 series (ie-78000-r or ie-78000-r-a), your in-circuit emulator can be upgraded to be equivalent to the ie-78001-r-a in-circuit emulator by simply replacing the break board with the ie-78001-r-bk (under development). table a-1. upgrading former in-circuit emulator for 78k/0 series to ie-78001-r-a in-circuit emulator cabinet upgrading note board to be purchased ie-78000-r required ie-78001-r-bk ie-78000-r-a not required note to upgrade your cabinet, bring it to nec.
289 appendix a development tools dimensions of conversion adapter (tgf-080rap) figure a-2. dimensions of tgf-080rap (reference) item millimeters inches b c a d e f g item millimeters inches b 14.1 0.555 c 0.8x15=12 0.031x0.591=0.472 a 20.65 0.813 d h i 10.0 0.394 23.6 0.929 j 12.4 0.488 e 16.4 0.646 f 18.8 0.740 k 14.8 0.583 l 17.2 0.677 m q c 2.0 c 0.079 r 18.65 0.734 13.35 0.526 s n 20.5 0.807 o 27.05 p 0.8 0.031 1.065 w x y t u v z 0.8 0.8x23=18.4 0.031 0.031x0.906=0.724 g 21.2 0.835 note : product of tokyo eletech corporation. 1.325 0.052 19.75 0.778 23.55 0.927 27.05 1.065 10.6 0.417 17.1 0.673 1.125 0.044 14.40 0.567 18.8 0.740 20.65 0.813 9.5 0.374 1.8 0.071 3.55 0.140 5.3 0.209 5.0 0.197 0.9 0.035 0.3 0.012 q 3.5 0.138 r 2.0 0.079 0.25 0.010 s n 7.35 0.289 o 1.2 p 1.85 0.073 0.047 w t u v 7.7 (16.95) 0.303 (0.667) 4- 1.3 4- 0.051 13.6 0.535 1.2 0.047 2.7 0.106 2.4 0.094 h i j k l m g tgf-080rap-g0 d p q a b c r s tt y i d e f z a i j k l k w v l u u s r q n p m o h g f e m n o x w u b c v v j t protrusion height h f ff f ff ff ff
290 [memo]
291 appendix b embedded software for efficient development and maintenance of the m pd780973 subseries, the following embedded software products are available. real-time os (1/2) rx78k/0 rx78k/0 is a real-time os conforming with the m itron specifications. real-time os tool (configurator) for generating nucleus of rx78k/0 and plural information tables is supplied. used in combination with an optional assembler package (ra78k/0) and device file (df780974). real-time os is a dos-based application. use dos prompt in windows. part number: m s rx78013- dddd caution when purchasing the rx78k/0, fill in the purchase application form in advance and sign the user agreement. remark and dddd in the part number differ depending on the host machine and os used. m s rx78013- dddd dddd product outline upper limit of mass-production quantity 001 evaluation object do not use for mass-produced products. 100k object for mass-produced product 0.1 million units 001m 1 million units 010m 10 million units s01 source program source program for mass-produced object host machine os supply medium aa13 pc-9800 series windows japanese version notes 1, 2 3.5-inch 2hd fd ab13 ibm pc/at and compatibles windows japanese version notes 1, 2 3.5-inch 2hc fd bb13 windows english version notes 1, 2 3p16 hp9000 series 700 hp-ux (rel. 9.05) dat (dds) 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news (risc) news-os (rel. 6.1) 3.5-inch 2hc fd notes 1. dos is also supported. 2. windowsnt is not supported.
292 appendix b embedded software real-time os (2/2) mx78k0 m ltron specification subset os. nucleus of mx78k0 is supplied. os this os performs task management, event management, and time management. it controls the task execution sequence for task management and selects the task to be executed next. mx78k0 is a dos-based application. use dos prompt in windows. part number: m s mx78k0- ddd remark and ddd in the part number differ depending on the host machine and os used. m s mx78k0- ddd ddd product outline note 001 evaluation object use for trial product. object for mass-produced product use for mass-produced product. s01 source program can be purchased only when object for mass-produced product is purchased. host machine os supply medium aa13 pc-9800 series windows japanese version notes 1, 2 3.5-inch 2hd fd ab13 ibm pc/at and compatibles windows japanese version notes 1, 2 3.5-inch 2hc fd bb13 windows english version notes 1, 2 3p16 hp9000 series 700 hp-ux (rel. 9.05) dat (dds) 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news (risc) news-os (rel. 6.1) 3.5-inch 2hc fd notes 1. dos is also supported. 2. windowsnt is not supported.
293 appendix c register index c.1 register index (in alphabetical order with respect to register name) [a] a/d conversion result register (adcr1) 150 a/d converter mode register (adm1) 152 analog input channel specification register (ads1) 153 asynchronous serial interface mode register (asim) 167, 171, 172 asynchronous serial interface status register (asis) 169, 173 [b] baud rate generator control register (brgc) 169, 174 [c] capture pulse control register (crc0) 104 capture register 00 (cr00) 102 capture register 01 (cr01) 102 capture register 02 (cr02) 102 clock output selection register (cks) 146 compare control register 1 (mcmpc1) 217 compare control register 2 (mcmpc2) 217 compare control register 3 (mcmpc3) 217 compare control register 4 (mcmpc4) 217 compare register 10 (mcmp10) 215 compare register 11 (mcmp11) 215 compare register 20 (mcmp20) 215 compare register 21 (mcmp21) 215 compare register 30 (mcmp30) 215 compare register 31 (mcmp31) 215 compare register 40 (mcmp40) 215 compare register 41 (mcmp41) 215 [d] d/a converter mode register (dam1) 163 [e] eeprom write control register (eewc) 69 8-bit compare register 1 (cr1) 112 8-bit compare register 2 (cr2) 121 8-bit compare register 3 (cr3) 121 8-bit counter 1 (tm1) 112 8-bit counter 2 (tm2) 121 8-bit counter 3 (tm3) 121 8-bit timer mode control register 1 (tmc1) 114 8-bit timer mode control register 2 (tmc2) 123 8-bit timer mode control register 3 (tmc3) 123
294 appendix c register index external interrupt falling edge enable register (egn) 231 external interrupt rising edge enable register (egp) 231 [i] interrupt mask flag register 0h (mk0h) 229 interrupt mask flag register 0l (mk0l) 229 interrupt mask flag register 1l (mk1l) 229 interrupt request flag register 0h (if0h) 228 interrupt request flag register 0l (if0l) 228 interrupt request flag register 1l (if1l) 228 [l] lcd display control register (lcdc) 193 lcd display mode register (lcdm) 192 lcd timer control register (lcdtm) 203 [m] memory size switching register (ims) 258 [o] oscillation stabilization time select register (osts) 246 oscillator mode register (oscm) 91 [p] port 0 (p0) 75 port 1 (p1) 76 port 2 (p2) 77 port 3 (p3) 78 port 4 (p4) 79 port 5 (p5) 80 port 6 (p6) 81 port 8 (p8) 82 port 9 (p9) 83 port mode control register (pmc) 217 port mode register 0 (pm0) 84 port mode register 2 (pm2) 84 port mode register 3 (pm3) 84 port mode register 4 (pm4) 84 port mode register 5 (pm5) 84 port mode register 6 (pm6) 84, 147 port mode register 8 (pm8) 84 port mode register 9 (pm9) 84 power-fail compare mode register (pfm) 154 power-fail compare threshold value register (pft) 154 prescaler mode register (prm0) 105, 232 priority specify flag register 0h (pr0h) 230 priority specify flag register 0l (pr0l) 230 priority specify flag register 1l (pr1l) 230 processor clock control register (pcc) 90 pull-up resistor option register (pu0) 87
295 appendix c register index [r] receive buffer register (rxb) 166 [s] serial i/o shift register (sio) 184 serial operation mode register (csim) 185, 186 16-bit timer mode control register (tmc0) 103 16-bit timer register (tm0) 102 sound generator amplitude register (sgam) 210 sound generator buzzer control register (sgbr) 209 sound generator control register (sgcr) 207 [t] timer clock select register 1 (tcl1) 113 timer clock select register 2 (tcl2) 122 timer clock select register 3 (tcl3) 122 timer mode control register (mcntc) 216 transmit shift register (txs) 166 [w] watch timer mode control register (wtm) 135 watchdog timer clock select register (wdcs) 141 watchdog timer mode register (wdtm) 142
296 appendix c register index c.2 register index (in alphabetical order with respect to register symbol) [a] adcr1 : a/d conversion result register 150 adm1 : a/d converter mode register 152 ads1 : analog input channel specification register 153 asim : asynchronous serial interface mode register 167, 171, 172 asis : asynchronous serial interface status register 169, 173 [b] brgc : baud rate generator control register 169, 174 [c] cks : clock output selection register 146 cr00 : capture register 00 102 cr01 : capture register 01 102 cr02 : capture register 02 102 cr1 : 8-bit compare register 1 112 cr2 : 8-bit compare register 2 121 cr3 : 8-bit compare register 3 121 crc0 : capture pulse control register 104 csim : serial operation mode register 185, 186 [d] dam1 : d/a converter mode register 163 [e] eewc : eeprom write control register 69 egn : external interrupt falling edge enable register 231 egp : external interrupt rising edge enable register 231 [i] if0h : interrupt request flag register 0h 228 if0l : interrupt request flag register 0l 228 if1l : interrupt request flag register 1l 228 ims : memory size switching register 258 [l] lcdc : lcd display control register 193 lcdm : lcd display mode register 192 lcdtm : lcd timer control register 203 [m] mcmp10 : compare register 10 215 mcmp11 : compare register 11 215 mcmp20 : compare register 20 215 mcmp21 : compare register 21 215 mcmp30 : compare register 30 215 mcmp31 : compare register 31 215
297 appendix c register index mcmp40 : compare register 40 215 mcmp41 : compare register 41 215 mcmpc1 : compare control register 1 217 mcmpc2 : compare control register 2 217 mcmpc3 : compare control register 3 217 mcmpc4 : compare control register 4 217 mcntc : timer mode control register 216 mk0h : interrupt mask flag register 0h 229 mk0l : interrupt mask flag register 0l 229 mk1l : interrupt mask flag register 1l 229 [o] oscm : oscillator mode register 91 osts : oscillation stabilization time select register 246 [p] p0 : port 0 75 p1 : port 1 76 p2 : port 2 77 p3 : port 3 78 p4 : port 4 79 p5 : port 5 80 p6 : port 6 81 p8 : port 8 82 p9 : port 9 83 pcc : processor clock control register 90 pfm : power-fail compare mode register 154 pft : power-fail compare threshold value register 154 pm0 : port mode register 0 84 pm2 : port mode register 2 84 pm3 : port mode register 3 84 pm4 : port mode register 4 84 pm5 : port mode register 5 84 pm6 : port mode register 6 84, 147 pm8 : port mode register 8 84 pm9 : port mode register 9 84 pmc : port mode control register 217 pr0h : priority specify flag register 0h 230 pr0l : priority specify flag register 0l 230 pr1l : priority specify flag register 1l 230 prm0 : prescaler mode register 105, 232 pu0 : pull-up resistor option register 87 [r] rxb : receive buffer register 166 [s] sgam : sound generator amplitude register 210 sgbr : sound generator buzzer control register 209
298 appendix c register index sgcr : sound generator control register 207 sio : serial i/o shift register 184 [t] tcl1 : timer clock select register 1 113 tcl2 : timer clock select register 2 122 tcl3 : timer clock select register 3 122 tm0 : 16-bit timer register 102 tm1 : 8-bit counter 1 112 tm2 : 8-bit counter 2 121 tm3 : 8-bit counter 3 121 tmc0 : 16-bit timer mode control register 103 tmc1 : 8-bit timer mode control register 1 114 tmc2 : 8-bit timer mode control register 2 123 tmc3 : 8-bit timer mode control register 3 123 txs : transmit shift register 166 [w] wdcs : watchdog timer clock select register 141 wdtm : watchdog timer mode register 142 wtm : watch timer mode control register 135
299 appendix d revision history the revision history of this edition is listed below. chapter indicates the chapter of the previous edition where the revision was made. (1/2) edition revisions chapter second table 2-1. pin input/output circuit types chapter 2 pin function correction of ports 8 and 9 input/output circuit types figure 2-1. i/o circuits of pins change of type 17-a to type 17-g addition of oscillator mode register to table 3-5. special function chapter 3 cpu architecture register list 4.1 eeprom functions chapter 4 eeprom change of the number of rewrite frequency per 1 byte as follows: 10,000 times ? 100,000 times 5.2.3 port 2 chapter 5 port functions ? correction of description ? correction of figure 5-4. p20 to p27 block diagram 5.2.4 port 3 ? correction of description ? correction of figure 5-5. p30 to p37 block diagram 5.2.8 port 8 ? correction of description ? addition of figure 5-9. p81 block diagram ? correction of figure 5-10. p82 to p87 block diagram 5.2.9 port 9 ? correction of description ? correction of figure 5-11. p90 to p97 block diagram table 5-3. port mode register and output latch settings when using alternate functions ? change of p setting values of p20 to p27 and p30 to p37 from 0 to ? change of note 2 addition of note in figure 5-13. port mode register (pm2, pm3) format ? addition of oscillator mode register to table 6-1. clock generator chapter 6 clock generator configuration ? change of figure 6-1. clock generator block diagram ? addition of (2) oscillator mode register (oscm) to 6.3 clock generator control register ? addition of explanation of oscillator mode register to 6.5 operation of clock generator 13.6 cautions on emulation chapter 13 a/d converter change of in-circuit emulator of (1) d/a converter mode register (dam1) as follows: ie-78001-r-a ? ie78k0-ns addition of (2) a/d converter of ie-780974-ns-em1 16.9 cautions on emulation chapter 16 change of in-circuit emulator of (1) lcd timer control register (lcdtm) lcd controller/driver as follows: ie-78001-r-a ? ie78k0-ns
300 appendix d revision history (2/2) edition revisions chapter second 17.1 sound generator function chapter 17 correction of description on (1) basic cycle output signal sound generator (with/without amplitude) 18.2 meter controller/driver configuration chapter 18 addition of cautions to (1) free running up counter (mcnt) meter controller/driver table 20-1. halt mode operating status chapter 20 correction of halt mode operating status of a/d converter standby function operable ? operation stops addition of oscillator mode register to table 21-1. hardware status chapter 21 reset function after reset change of note in table 22-1. differences between m pd78f0974 and chapter 22 m pd78f0974 m pd780973(a) ? support of in-circuit emulator ie-78k0-ns appendix a development ? change in supported os tools ? addition of a.4 upgrading former in-circuit emulator for 78k/0 series to ie-78001-r-a ? deletion of os for ibm pc from previous edition ? deletion of development environment when using ie-78000-r-a from previous edition ? change in supported os appendix b ? deletion of fuzzy inference development support system from embedded software previous edition
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